Have a question about CadSoft EAGLE?  Ask our Expert, Richard! (Archive)

Hi John,

I am not quite sure what RINF format is. Is it supported by Orcad or Pad?

Basically there are several tools (ULPs) that allow exporting different formats. Please take a look into the CadSoft web site www.cadsoft.de/download.htm and check the ULP directory.

If you  use your browser's search function on the site, you will find different ULPs that might help.

Best regards,

Richard

Hi Michael,

in the manufacturing process of a board oblong holes, for example, will be milled. So you have to draw the milling contour manually in a separate layer, which is usually layer 46, Milling. Use a very fine wire width for the contour. Tell your board manufacturer that there are milling contours to take care of.

Regards,

Richard

Hi Jerome,

increasing the SMDImpact parameter should cause the Autorouter to draw the a longer trace  in preferred direction before there is a bend or a via. Did you set preferred directions? Did you increase the parameter for the Optimize passes as well?

Regards,

Richard

Hi,

I would like to know if it's possible to show the clearance between tracks while routing them as KiCAD does.

Also, can you move individual pads for a part manually without having to make a custom footprint?

Thanks in advance

Hello Richard,

I believe I found a solution to the problem I created using the following process.  But if there's a simpler way to accomplish the fix I'd like to have it.

1. I renamed the power plane from VDD_FLASH to  _VDD_FLASH which removed all of the power plane connections.

2. I then ripped up the traces leading to the two pins I needed to remove from the power net.

3. I then deleted the airwires going to those two pins.

4. Saved the job file.

5. Reran the script to reload the netlist into the board.

6. Ran the ratnest command and confirmed that the airwire for the two pins was now the N_CE2 net.

7. Renamed the power plane back to VDD_FLASH and ran DRC.

8. Rerouted the N_CE2 net, ran DRC, and verified that the net is still the N_CE2 net name.

I'll export the netlist from the board to verify that the netlist matches the script, but this does appear to have fixed the problem.  The trick appeared to be renaming the power plane to remove the automatic connections, so I could rip up the part of the net I needed to isolate.

Cheers,

Ralph

Hello Richard,  I have a simple issue that I'm stuck on. I've finished routing a four layer board, and somehow managed to connect a chip enable net, N_CE0 to the power plane net, VDD_FLASH.  I need to remove two pins from the power net and recreate the chip enable net.  I've tried deleting the routs and airwires for the chip enable net, and entering the netlist again with no luck.  Can you tell me how to correct my problem?

Thanks in advance for any help you can provide.

Cheers,

Ralph

Richard,

I need to generate some net lists from and existing design.  In particular, I need to generate a RINF format netlist, and probably some others.  Can you point me in the right direction?  There seems to be a lack of documentaiton on netlists and output files other than some scripts here and there.  Is there a manual or something I'm missing?  I'm relatively new to Eagle but old to PCB CAD.

Hi,

   Can you explain how --if at all possible -- to create a square/rectangular mounting hole using Eagle?

Thanks, Michael

Hello,

When using the autorouter, why the "SmdImpact" parameter does not matter if the autorouter decides to place a via ? The autorouter places a via very close to the SMD, and then it cannot routes the other signals... It is really annoying and time consuming...

Thank you.

Hi,

EAGLE can handle them. There are some card edge connectors in the EAGLE libraries, for example in con-pc.lbr.

HTH

Regards,

Richard