Hi,
I got some confusions about PCIex4 routing. Some people say there should not be any vias on RX and TX and some says it can be allowed. Which is correct?
Hi,
I got some confusions about PCIex4 routing. Some people say there should not be any vias on RX and TX and some says it can be allowed. Which is correct?
You usually route PCIe TX on top and RX on bottom, so you need vias and the spec allows for it. As in your table, it is recommended that the max pad is 25mil and hole is 14mil. Also, vias should be in pairs, if you pop a via in RX+, there should be a via in RX- and they should be close to each other. Vias should only be at the end points and not in the middle of the trace. Pads on inner layers should not connect to the via.
That answer can be found here as they make the specifications.