Am I on the right track (DRC settings for 0.8mm BGA PCB)?

Having been in about the same situation earlier this year I can offer what's worked for me so far. However I have not used BGAs but I did just do two boards with a QFN package where the pads are 0.25mm wide on 0.50mm centers. Can't say what I did is right/best, but it worked for me and the PCB house I'm using (PCBWay).  I would suggest though as a first step is see what your board house prefers - and what they charge extra for.

• For signal traces (with the QFN)  I set min/pref/max to 0.2, 0.25, and 0.3 mm respectively. I set all of my clearances to 0.2mm.
• I also assigned net class to all of my power nets (the boards are 2 or 4 layer for cost reasons and there's a handful of digital and analog supply voltages) and on the top layer did 0.2, 0.5. and 2.0 mm so that way I could run power to pins easily. On the other layers (all my components are on the top so routing density is the worst there) I made the minimum size larger as well as a huge max size (6 mm) so I could run large "bus" power across the board if needed.
• As I didn't have a cramped design. I left my vias large (0.6mm hole and 1.1mm diameter), Holes < 0.3mm raise the board price at my vendor.  I also had different via rules for the power nets, 0.8 hole and 1.4mm diameter.
• I can't pretend to understand the details, but the IPC footprints come in 3 different densities. As I was hand assembling prototypes I found that the high density footprints (which have smaller pad sizes) were a pain to deal with. As for what assembly houses can deal with you will need to check with whomever you plan to use. However so far I have found that the pick and place programming is pretty "smart" in terms of the order parts gets placed, etc.  I think about it more in terms of "if I had to get at that part during debug, can I?" The 3D views have helped me considerably in not being too dumb in placement.
• IMHO you really want something that tells you which pads a part goes across - again for me it was my concerns about building the prototypes by hand, but I have since learned that the assembler likes it too so they can visually verify the programming, etc. I've seen two styles, one with a line perpendicular to the component body, and the other as two dots (or short line segments for larger parts > 0805) between the pads.  I do find that these break the DRC rules you might normally want to have for the overlay silk to solder mask clearances; they are tiny but it has not been a problem with the PCB fab.  I really now just check for silk actually on the pad.

As an aside I set everything for metric units in the PCB editor. The only place I stuck to mils was for the component package size names, as many (passive) component vendors follow that still.

I can imagine though with a BGA the above isn't going to help even though I had a QFN with a tighter pitch.

Good luck.

My 2c:

The values you've given all look very sensible.

Removing the silkscreen is generally acceptable, something I've done many times is to leave the silkscreen off altogether when the PCB is manufactured, but include it in assembly drawings for reference.

As far as distance between components goes, this is entirely down to the method of assembly - I have my own pick and place machine which will happily place components with a 0.2mm gap.  If you're hand-soldering you'll need enough room to get an iron onto the component pins/pads.  BTW if you're using paste and reflow then smaller pads are desirable since the components will tend to self-centre as the solder melts.

Although it's fine to go to 5mil for signal tracks, be careful not to skimp on power tracks; if you need to neck down to get to a pin/ball then do it as close to the package as possible.  I'd imagine for the operating speed you're looking at you might well want to use 4 or 6 layers with at least a ground plane and possibly a power plane too.

Thanks a lot for the insight.  I currently am trying to do it on 4 layers.  I'm using the bottom layer for the power planes and am doing fills for the routing versus traces to keep those tracks nice and thick, only doing 5 mils (0.127mm) for the signals to have enough clearance through the BGA ball pads.  The problem is the bypass caps.  There are about 54 of them that I have to place and route to about 62 Vdd pins just for the MPU and DDR2 memory chip.  Fortunately, most of them are clustered toward the center.  I guess I also need to pick a board manufacturer to be sure about some of the settings.

Some designers put bypass caps on the back of the PCB, often in an attractive pattern.  Others suggest that the inductance of vias is undesirable, although speaking for myself it's hard to see how a 1.6mm long via is worse than a 5mm track.  And of course if you're going to connect a cluster of power pins together you'll want multiple vias to keep the impedance low.