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Plane Clearance Issue

batuu

I have a design with high voltage nets. Therefor I have defined a Net Class "HV_NET" with the members NETZ_L1A, NETZ_L1B and NETZ_N.

I want to connect the net  "NETZ_L1A" on the Plane 1 layer. The clearance for my HV_NET class should be 3mm, so I created a design rule named "Clearance_HV_NET_3.0" for this.

I also created the power plane clearance rule "Plane_Clearence_HV_NET_3.0".

 

The result is the following. The split plane is assigned to the net "NETZ_L1A". The clearance around the pins with the net NETZ_N are correct. Why there is no clearance around the PE pins and the big PE mounting hole in the upper left.

I get the right result if I assign PE to the HV_NET class, but I do not want to, because then every via like the ones in the right (in the GND split plane area) would get a 3mm clearance.

With my rule set I do not get any design rule check error despite clearance violation between NETZ_L1A and PE.

 

Any thoughts how to handle this issue? Am I missing something?

 

Best regards,

Oliver

 

CS v1.5.2

 

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  • 0

    My suggestion would be to set the default plane clearance to 3mm and remove your custom rule. The rule you added means that the place should clear between itself and the new class specified which it has done, all the other clearances use the default rule.

  • 0 in reply to e14softwareuk

    Hallo Peter,

     

    thanks for your suggestion. Sadly this is not what I want.

    With just the default  plane clearance rule set to 3mm I'm getting this:

    image

    I only want the selected area (HV net) within the green box to have a clearance of 3mm to any other net. The split plane outside of the box is GND. I do not want all the PE vias to have a 3mm clearance too.

    Why the electrical clearance rule do not apply for the internal plane layers?

     

    Oliver

  • 0 in reply to batuu

    Hi Oliver. I think you will need to switch to drawing your split plane using polygons on a copper layer to be able to configure the design rules needed for this. Create a couple of polygons and name them (e.g. HV, LV), create two polygon classes (one polygon per class) and then add two new Electrical Clearance design rules (one per polygon class). This will give you control over the clearance in each region. To make sure the HV polygon generates the cutout from the larger LV polygon use right click Polygon Actions > Bring To Front so the HV one is processed first.