I have a multi-channel design using hierarchical sheets and the Repeat() operator. I have two banks of two channels for a total of four channels. Each channel needs a USB DP/DN pair connected from the top level. As far as I can tell this is impossible despite being a fairly common requirement. The multi-channel feature requires the appending of _1,_2,_3,_4 to the net names and the Differential pair feature requires the appending of _P,_N to the net names. I end up with a bunch of compile errors.
Is there any way around this or is it just an inherent limitation of Circuit Studio?
Class Document Source Message Time Date No.
[Error] Top_Level.SchDoc Compiler Missing Negative Net for differential pair [USB_D_P_1_1], positive net [USB_D_P_1_1_P] 4:46:18 PM 7/12/2022 13
[Error] Top_Level.SchDoc Compiler Missing Negative Net for differential pair [USB_D_P_1_2], positive net [USB_D_P_1_2_P] 4:46:18 PM 7/12/2022 14
[Error] Top_Level.SchDoc Compiler Missing Negative Net for differential pair [USB_D_P_2_1], positive net [USB_D_P_2_1_P] 4:46:18 PM 7/12/2022 15
[Error] Top_Level.SchDoc Compiler Missing Negative Net for differential pair [USB_D_P_2_2], positive net [USB_D_P_2_2_P] 4:46:18 PM 7/12/2022 16
[Error] Top_Level.SchDoc Compiler Missing Positive Net for differential pair [USB_D_N_1_1], negative net [USB_D_N_1_1_N] 4:46:18 PM 7/12/2022 17
[Error] Top_Level.SchDoc Compiler Missing Positive Net for differential pair [USB_D_N_1_2], negative net [USB_D_N_1_2_N] 4:46:18 PM 7/12/2022 18
[Error] Top_Level.SchDoc Compiler Missing Positive Net for differential pair [USB_D_N_2_1], negative net [USB_D_N_2_1_N] 4:46:18 PM 7/12/2022 19
[Error] Top_Level.SchDoc Compiler Missing Positive Net for differential pair [USB_D_N_2_2], negative net [USB_D_N_2_2_N] 4:46:18 PM 7/12/2022 20
[Error] Top_Level.SchDoc Compiler Net USB_D_N_1_1_N has only one pin (Pin IC1-1) 4:46:18 PM 7/12/2022 21
[Error] Top_Level.SchDoc Compiler Net USB_D_N_1_1 has only one pin (Pin X1_J6-30) 4:46:18 PM 7/12/2022 22
[Error] Top_Level.SchDoc Compiler Net USB_D_N_1_2_N has only one pin (Pin IC1-3) 4:46:18 PM 7/12/2022 23
[Error] Top_Level.SchDoc Compiler Net USB_D_N_1_2 has only one pin (Pin X3_J6-30) 4:46:18 PM 7/12/2022 24
[Error] Top_Level.SchDoc Compiler Net USB_D_N_2_1_N has only one pin (Pin IC1-6) 4:46:18 PM 7/12/2022 25
[Error] Top_Level.SchDoc Compiler Net USB_D_N_2_1 has only one pin (Pin X2_J6-30) 4:46:18 PM 7/12/2022 26
[Error] Top_Level.SchDoc Compiler Net USB_D_N_2_2_N has only one pin (Pin IC1-8) 4:46:18 PM 7/12/2022 27
[Error] Top_Level.SchDoc Compiler Net USB_D_N_2_2 has only one pin (Pin X4_J6-30) 4:46:18 PM 7/12/2022 28
[Error] Top_Level.SchDoc Compiler Net USB_D_P_1_1_P has only one pin (Pin IC1-2) 4:46:18 PM 7/12/2022 29
[Error] Top_Level.SchDoc Compiler Net USB_D_P_1_1 has only one pin (Pin X1_J6-28) 4:46:18 PM 7/12/2022 30
[Error] Top_Level.SchDoc Compiler Net USB_D_P_1_2_P has only one pin (Pin IC1-4) 4:46:18 PM 7/12/2022 31
[Error] Top_Level.SchDoc Compiler Net USB_D_P_1_2 has only one pin (Pin X3_J6-28) 4:46:18 PM 7/12/2022 32
[Error] Top_Level.SchDoc Compiler Net USB_D_P_2_1_P has only one pin (Pin IC1-7) 4:46:18 PM 7/12/2022 33
[Error] Top_Level.SchDoc Compiler Net USB_D_P_2_1 has only one pin (Pin X2_J6-28) 4:46:18 PM 7/12/2022 34
[Error] Top_Level.SchDoc Compiler Net USB_D_P_2_2_P has only one pin (Pin IC1-9) 4:46:18 PM 7/12/2022 35
[Error] Top_Level.SchDoc Compiler Net USB_D_P_2_2 has only one pin (Pin X4_J6-28) 4:46:18 PM 7/12/2022 36
The hub sub-sheet with the differential pair definitions
The mid level of the hierarchy of sheets (bottom level of hierarchy is not shown but is similar)
The top level
