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Possible to generate a netlist from Circuit Studio?

jmarkwolf

Many years ago, I wrote a custom program for reporting missing test points in Altium/Protel net lists. It worked very well and used it often.

A new client has asked me to add test points to every net in a Circuit Studio design.

Now that I no longer have access to Altium I can't use my old tried and true program to report missing test points.

Is it possible to generate just a net list from a Circuit Studio SchDoc, or am I hosed?

  • I may have answered my own question.

     

    I see that I can generate a net list from the PCB side with "Tools/Netlist/Export net list from PCB". I can probably make this work.

     

    The SCH side doesn't seem to have the equivalent command. Anyone know a work around for the SCH side?

  • in reply to jmarkwolf

    You can export an EDIF netlist from a schematic (Outputs | EDIF for PCB)

  • in reply to e14softwareuk

    This brings up a question from me.  In the properties for pads/vias there are check boxes for testpoint settings to assign the pad as a fabrication or assembly testpoint on top or bottom layer.  What does the selection of these actually do?

     

    image

    These seem to be like what Altium Designer used to assign test points which would then link into Altium Designer pcb rules and its Testpoint Manager.  However, CircuitStudio lacks those features of AD.  In CircuitStudio, is there any other use for setting the testpoint settings boxes?

     

    Also, I typically prefer generating ODB++ output over Gerbers.  ODB++ should have testpoint information.  But if I do generate Gerber plots, how can I generate a test point output for IPC-D-356?

  • in reply to tarribred61

    CS does not support IPC-D-356 output generation.

  • in reply to e14softwareuk

    Update:

     

    It turns out that the net list format generated by the PCB/Tools/Netlist/Export is the same old Protel netlist format that my custom program was written for, so my old program is good as-is! image

     

    It would be more convenient if the net list could be generated from the SCH side, but I can live with it. I just have to be sure to remember to update the PCB prior to exporting the net list and analyze for missing test points.

     

    The reason I do it this way is that I create a Test Point schematic component and PCB footprint and place at least one on each net on my SchDoc. They're designated as "Standard (No BOM)" so they don't clutter the BOM. These entities can be assigned attributes for standard DRC rules like any other component. This allows a DRC rules specific for the test points to make sure they aren't too close to each other, etc.

     

    The more I use Circuit Studio, the less I miss Altium Designer!