How do I create a custom pad shape?

jaza_tom  wrote:

I have created a solid region of the shape I desire.  How do I specify the solder and paste mask expansion values for this shape?

You draw them on the corresponding layers.

For Paste you draw them on Top(Bottom) Paste layer, for soldermask you draw on Top(Bottom) solder layer.

Let's say you have a T-shape drawn on Top layer. To make it easier you can copy the shape and change the copy's layer to Top Solder (double click the shape and from there change the layer). Shapes drawn on the soldermask layer are negative, meaning the drawn shapes are actually openings.

Now, you want the soldermask opening to be bigger than the actual "custom pad" so you need to scale it (inflate it). To my knowledge there is no such a thing in CS so you need to do it again, manually.

Change the grid to a finer one (a good start could be: if you drawn your custom pad on a 1mm grid then the finer grid could be 0.1mm) and start dragging the vertexes to outside as much as you want your soldermask to expand. Then center the shape on Top Layer (your custom pad) with the newly created soldermask opening.

Same for solder paste but in this case you want to "deflate" the shape because the shapes drawn on Top(Bottom) Paste are positive (where you draw you have solderpaste filling).

jaza_tom  wrote:

How do I designate this shape as being a "pad", so that I can associate schematic symbol pins to it?

After you made your custom shape, you make a tiny pad (using the "Pad" menu entry; can be round, square, doesn't matter)  that can be superimposed over your custom pad. Usually is placed in the geometrical center of your custom shape. It will be the "connection point' for the traces.

You can double click on it and change the designator and maybe remove the soldermask and pastemask for this tiny pad by setting the expansion value with negative values; if the tiny pad is a circle with 0.1mm size then you can write -0.1mm in the expansion entry fields.

I let the tiny pad above the custom pad so you can see it. Observe that there are no soldermask openings for it (purple color) around it. As a final action, this tiny pad would need to be moved over the custom shape, in the center.

I made it oblong (doesn't matter) to be visible in this picture.

Thanks bahd!

Hi Marius, wish I had your post before I had tried to figure that out.  I'm curious if you've dealt with adding vias to a pad under a QFN, i.e. the area is meant to be grounded as well as thermally tied to as much copper as possible. I've been able to get the vias in and adjust the solder mask to not cover them, but it seems like something in the DRC doesn't like what I've done - it's been a while but I think the via spacing trips it up as it doesn't think it's all tied together ?  I work around it by adding a rule for the footprint but it would be nice to either understand how to add vias to the footprint in way that the DRC is happy with or include some sort of info in the footprint that tells the DRC to skip it (not sure that's possible, as while layout has a pad class property doesn't seem to be any way to use it?).

Thanks

lamabrew  wrote:

 

I've been able to get the vias in and adjust the solder mask to not cover them

Why would would you not want solder mask covering these vias?  If you do not have solder mask on these vias, then they will get soldered to the bottom of your QFN chip when it comes time to assemble the board...

oops, my bad. I meant to say: adjust the solder mask so that it surrounds the pad and the stencil so that paste is not in the via area (as per manufacturer's recommendations). Like this:

Actually there are at least a few reasons for not wanting soldermask under the IC:

- soldermask can "bubble" (never happened to me, I just hear about it) when the reflow is done and can raise the IC. Might apply for BGA's /lead-free solder only or larger IC's ...

- you want the IC thermal pad to make the best contact with the PCB for better heat dissipation

- soldermask is not perfectly flat and can raise the IC a bit (very unlikely for a fab work but still a possibility if you do the PCB at home - like I do when I do hobby)

Hi Marius, wish I had your post before I had tried to figure that out.  I'm curious if you've dealt with adding vias to a pad under a QFN, i.e. the area is meant to be grounded as well as thermally tied to as much copper as possible. I've been able to get the vias in and adjust the solder mask to not cover them, but it seems like something in the DRC doesn't like what I've done - it's been a while but I think the via spacing trips it up as it doesn't think it's all tied together ?  I work around it by adding a rule for the footprint but it would be nice to either understand how to add vias to the footprint in way that the DRC is happy with or include some sort of info in the footprint that tells the DRC to skip it (not sure that's possible, as while layout has a pad class property doesn't seem to be any way to use it?).

 

Thanks

LE: are you talking about adding vias under QFN while doing the layout or when creating the footprint?

Cool, good to know!

I thought that lamabrew was talking about routing vias for other signals underneath the QFN pad.

Hi Marius,

Boy my earlier convoluted comment made a mess of the thread...sorry for the confusion. I am referring to adding vias in the ground/thermal pad under the QFN, and fighting with the DRC to not have it flag all of the vias as violating clearance rules.

I went back and reminded myself how I fixed that - I was thinking I had set some rules based on the footprint but that was for a different part; I got the QFN to work by assigning the pad to the ground net. Not sure why connecting it with vias to ground didn't make it part of the net but that seems to have stopped the DRC errors.

I guess my question about putting something in the PCBLib footprint to tell DRC to skip certain things would still be a general question I have, though now that I write that out maybe it's always best to deal with that in the PCB tools if design rules are going to differ?

Thanks,

Brewster

mars01

Marius, do you know how to assign vias under QFN while doing footprint to a specific net (GND)? In the Net properties dialog for pads is always "No nets". Libraries are added (linked) to the project with multiple nets.