Hi,
I'm working on a 6-layer PC with buried vias and microvias, so I have design rules for the different layer pairs (1-2, 2-5, 5-6, 1-6). Circuitstudio is complaining that 'Some rules have incorrect definitions" but without any clues as to what's up. Does anyone have any idea how I'd find and resolve the problem? Incidentally the board seems to track more or less properly, although ideally I'd have CS pick up the preferred via size that corresponds to the layers each via is going between - perhaps this will happen automatically once I get the rules sorted out.
Cheers,
Frog
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