Interested in Learning about Vivado?
If you are interested in Xilinx's products or are doing RoadTests of dev boards based on Xilinx's FPGA-based SoCs, I wanted to let you know about a virtual event on the Vivado Design Suite. It's a 2-day virtual event packed full of virtual presentations. This event is focused on learning more about the Vivado Design Suite. You'll learn how Vivado supplies design teams with tools and methodology needed to leverage integrated automation, IP subsystem re-use, and accelerated design closure.
What You Will Learn
- Learn how to leverage Xilinx’s Versal
platforms to achieve the shortest time-to-market. - Master the collaborative features of IPI which enable higher productivity in various parts of the design cycle.
- Learn how Dynamic Function eXchange can allow designers to move to fewer or smaller devices, reduce power, and improve system upgradability.
- Discover the latest developments in the design closure (methodology, timing, and power), and pick up the collection of best practices based on the experience of factory experts, helping to achieve the best QoR on the toughest designs.
Here's the Agenda:
February 10, 2021 (all times are PST)
- Keynote - Hardware Development Strategy 8:00 AM-8:30 AM
- Getting Started with the Versal Architecture 8:30 AM-9:00 AM
- Collaborative and Accelerated Design with Vivado IP Integrator 9:00 AM-10:00 AM
- Dynamic Function eXchange 10:00 AM-10:45 AM
- Add-on for MATLAB
and Simulink 10:45 AM-11:15 AM
February 11, 2021 (all times are PST)
- High-Level Synthesis 8:00 AM-8:30 AM
- Design Closure: Methodology, Tips, and Tricks for Achieving Better Quality-of-Results (QoR) 8:30 AM-9:30 AM
- Design Closure: Using Timing Closure Assistance Tools to Address Tough Timing Issues 9:30 AM-10:15 AM
- Design Closure: Power Constraints, Best Practices for an Accurate Report Power Estimation 10:15 AM-11:00 AM
- Simulation and Hardware Debug 11:00 AM-11:30 AM
