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Ideas: Capturing Data into RAM/BRAM/DDR3?

14rhb

I would be really grateful for some initial ideas from the FPGA/E14 experts as to how I can do the following: I'm happy to struggle on learning and writing the scripts needed but I really haven't got an idea which method should be used. This learning is for my Z7k Logic Analyser: concepts where I eventually want to be able to capture the voltage changes on some input pins at a very high clock rate (say 100MHz) directly into RAM and in slower time to be able to sift through them using the PS to do analysis - for example to display the hexadecimal equivalent or if it were UART data to give the user the values in that.

 

I've explored the idea of BRAM and being able to read/write to it from the PS: Z7k Logic Analyser: progress update and I've also just managed to follow an online tutorial where the author implements a FIFO to pass DMA data to and read it back from: Z7k Logic Analyser: Progress Update #2

 

My current thinking is that I need to make my own AXI-4 IP block, as previously, that fills up with the serial data. I'm also thinking that will be limited somewhat due to limitations in BRAM sizes whereas the DDR3 on the ZC702 is massive and could store so much more of the signal.

 

Does anyone please have any suggestions on what could be the better approach? Thank you.

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  • I can see that I can make an AXI-4 stream IP block and set the AXI-4 interface to master i.e. it could perhaps tell the DMA controller it is full (via the interrupt) and then the DMA takes the data and writes it to DDR3 RAM? Perhaps I can then edit the new IP block called myDataStream to save several bytes from the actual serial input before it issues the interrupt?

    image

    Would that sound like the right sort of approach?

  • in reply to 14rhb

    How about a FIFO (which will use BRAM) that accepts the incoming data, followed by an AXI DMA core? The AXI DMA core resides in the PL (different from the PS DMA), and can be configured to operate using descriptors (either in a BRAM or the main DDR), and send data from the FIFO to the DDR

  • in reply to avnrdf

    Thank you - that is just the sort of guidance I was hoping for. As a beginner I didn't really see the FIFO as BRAM (doh).

     

    So there will be two DMA controllers using the same DDR3 RAM? The one on the PS controlled via the Zynq and the new IP one that I place on the PS?

     

    In your knowledgable opinion, do you think the FIFO would need an interupt to the Zynq to signal it was full up or had some data ?

  • in reply to 14rhb

    I think that you wouldn't need the DMA controller in the PS,T but yes there will be 2 DMA controllers. The FIFO could send an interrupt when its filling up, which could trigger the AXI DMA.

    I think the descriptors will need to be setup from the PS, and then you either make the FIFO generate an IRQ to the PS which enables the DMA (the FIFO will buffer samples during this time), or find a way to trigger the DMA directly.

  • in reply to avnrdf

    Thank you again for your help in explaining this. Knowing a correct approach is great and I can then work out the finer wiring and code required. It also gives me the areas I need to concentrate on - I used the FIFO in an example for DMA but didn't really delve into how it worked....I'll read up on it now.

  • in reply to 14rhb

    Good to hear that this has answered some questions!

     

    I'm got a plan to build a logic analyzer for Zynq - so some of this is based on how I've planned mine!

     

    One way is to have a buffer/FIFO on the front which gives the DMA engine enough time to kick in when triggered.

    My plan is to have another custom HDL core in front of that which acts as a circular buffer so that I can capture data before the trigger point. I'm also looking at doing something smart with the DMA descriptors to get the same functionality.

     

    Lastly, look at the opensource HDL & firmware of the ADI M2K (which has a logic analyzer): https://wiki.analog.com/resources/fpga/docs/hdl/m2k

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  • in reply to 14rhb

    Good to hear that this has answered some questions!

     

    I'm got a plan to build a logic analyzer for Zynq - so some of this is based on how I've planned mine!

     

    One way is to have a buffer/FIFO on the front which gives the DMA engine enough time to kick in when triggered.

    My plan is to have another custom HDL core in front of that which acts as a circular buffer so that I can capture data before the trigger point. I'm also looking at doing something smart with the DMA descriptors to get the same functionality.

     

    Lastly, look at the opensource HDL & firmware of the ADI M2K (which has a logic analyzer): https://wiki.analog.com/resources/fpga/docs/hdl/m2k

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