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Using multiple Xilinx Series-7 transceivers from the same quad separately.

rachaelp

Hi All,

 

I've got a design using a Kintex-7 FPGA. I have a single channel transceiver up and running and I have tested that all the transceiver channels work in the board individually but now I am trying to get all four transceivers up and running at once and am having issues.

 

So I created the original transceiver with the 7-Series FPGAs transceiver wizard from the IP catalog, chose the protocol I need, clock rates, line rate, etc, included the shared logic in the core. I then wrote some initialization and monitoring state machines to control the transceiver and make sure it all comes up correctly and it works. So, when I wanted to scale this up to 4 identical but independent channels, I took a copy of the IP and changed it so it didn't include the shared logic in the core and instantiated 3 copies of this. I then hooked up all the out's from the original transceiver to the corresponding ins of the new transceivers to get all the shared clocking buried in the first instance connected up to the new instances. I then replicated all the state machines and slaved the ones for the new transceivers to the first so they don't start their initialization until all the clocking and everything is good on the first and that's up and running. It all builds and the first transceiver still works fine, but unfortunately none of the newly added transceivers do anything at all and their outputs are stuck at 0. Has anybody else here got experience with these transceivers and managed to get a similar setup working? Any pointers would be much appreciated!

 

Many thanks,

 

Rachael

  • 0

    Ok, so for anybody interested or who faces a similar issue in future, I managed to solve my problem.

     

    It turned out to be the choice of PLL within the block as I was trying to share the single incoming external diff clock with all the transceivers in the quad. In my original version I had the CPLL (Channel PLL) chosen for the transceiver reference clock source. When I created the duplicate without shared logic this selection got transferred over to these too. Except there is no valid clock source for the CPLL for these blocks in my design and I need to be using the QPLL (Quad PLL) which can be shared amongst all for transceivers in the quad. I swapped this over in the IP wizard for both transceiver types and tweaked the instantiations accordingly and it all sprang into life.

     

    Best Regards,

     

    Rachael