How does Tx Only Serial Communication Actually Work?

It is just a fire and forget transmission. The sender does not care or respond to what is happening  with the receiver. It depends on the receiver being ready and able to receive anything and everything that gets transmitted, whenever it gets transmitted.

Sometimes such devices can be configured for different baud rates or to have a longer delay between bytes to make it easier.

GPS modules are like this - if the receiver misses a byte or gets out of sync, the receiver must recover by looking at the data or the timing of the transmissions.

Data may be preceded by a synchronizing header that needs to be parsed, but often it is just preceded by a defined break in transmission data.

So, I take it when you are catching such transmission, you really have to be lean on what you do in between byte reads.

I'll have it look for a certain byte, turn on a flag to look for the second byte, and repeat until I have the series or reset if I it isn't what's expected.  Once the series is detected, I'll then trigger a routine to swallow the whole packet.

I never stop feeling amazed on how much these things can do in such a small fraction of time.  It's darn right divine.

Thanks for the tips.

See ya',

Sean

Serial bytes take a long time (measured in CPU instruction cycles) to receive a whole byte, so there is lots of time to deal with the last byte while the next one is arriving, assuming there is a UART receiving individual bits. But often the low level handler just collects a whole message in a buffer, in real time, while performing higher level parsing of complete messages in the background. Then the parsing routine just needs to be completed before the next complete message is received.

When the line is in idle its at 1, when it begins transmitting goes to 0 (start bit). The falling edge indicates the beginning of a byte transmission. So unless the transmitter is sending data at full speed, its straightforward to synch to the transmitter, as the line cant stay high for 10 or more time units, unless its in idle.

In I2C, you have the clock line to keep the beat and compare against.  With serial, how does the receiver know a zero since the edge already fell?

-Sean

The simple approach for 8n1 is to wait for 10 or more time units that line is high. That will tell you that the line is idle. At that moment you wait for falling edge (start bit) wich will tell you that byte transmission will begin.

So, when it falls low and signals the start bit, I picture that it will then a series of highs and lows.  Without a clock line to index each bit, how does the 8 bits of the byte about to transmit get received without getting confused when you have two Highs in a row or two Lows in a row?

Thanks,

Sean

Because you must know the timing (Actually there are timing algorithms too, but thats more complex). I recently implemented an UART receiver on my FPGA, so if you understand Verilog and have an FPGA I could share it with you. Usually algorithsm work kinda like this.

you run a clock at say 16 times the speed of 1 bit duration. So for instance if you plan to receive a signal of say 2400 bps, you need to sample at a rate of 38400. Here is an example of a signal 8N1 (8 data bit, no parity bit and 1 stop bit).

So you once you detect a falling edge, you will wait enough time to sample right in the middle of the bit1 and then bit2, and so on. If you want the receiver to be more robust you may want to sample multiple times every bit in order to avoid that transients corrupt your data. In the best case scenario a transient would just corrupt a single or very few samples from the bit. So for instance if you sample 5 times every bit, its likely that if a transient occured, it would flip just 1 or very few samples out of the 5 in total. The transmitter and receiver could use different clocks, and there could be a mismatch in their timing, but that shouldn't be an issue if you continuosly resync the clock.

Thanks so much!  It finally clicked for me.

I have trouble thinking in such small fractions of a second, but if I envision that chart scaled out to minutes, there is no doubt I could write a routine to poll the signal in all kinds of ways and feel confident I captured the timing of the highs and lows correct.  It's just that computers now for decades can perform such a function at freaky fast speeds with confidence.

As you state, the width of each expected pulse gives room for error when you target the middle.  Any rhythm or speed differences between the two device clocks will be reset after the 8th bit of each byte preventing drift over time.  It's really genius and so darn simple at the same time.  I love it.

Thanks so much for helping me get over the hump on this one.

-Sean