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Support required for HMC356LP3ETR Low-Noise Amplifier

alphaise
During probing of the IC, we observed that pins 6 (GND) and 7 (ACG) are shorted together, and are also shorted to pin 15 (Vdd). However, the other GND pins (ground paddle, pins 2, 4, and 16) do not appear to be shorted together.
This issue was observed consistently in 2 units that were tested. For reference, I have attached the pinout diagram and a top-view image of the IC.
image     image
  • 0

    Is this before or after you had applied power ?

    Where did you buy the parts ?

    How are you measuring them - when you say "shorted" what do you mean - is it the same resistance in either polarity, what is that resistance.

    MK

  • 0 in reply to Jan Cumps

    Yes, I checked against the chamfered edge on the ground paddle as well.

  • 0 in reply to michaelkellett

    The issue is consistent both before and after applying power.

    The parts were purchased from Element14 (Singapore), and they had sent over replacement units after I alerted them of the issue - but the shorting is still present (i.e., no change). 

    I used the continuity test on various multimeters for measurements. The resistance between pin 15 (Vdd) and 6 (GND) is about 8.1 Ω, and 2.9 Ω between pin 15 and 7 (ACG).

  • 0 in reply to alphaise

    What is the "issue"?

    The datasheet says the pins labelled as GND should be connected to RF/DC ground. It doesn't say they're all connected inside the device.

    The resistance you measure between 6 and 7 is the bias for the FET. You'd expect to see it there. Presumably you've connected a decoupling capacitor to 7 and not a GND in your circuit. If you've connected a ground to 7, you'll get whatever the FET current is with the gate at 0V, instead of the 100mA or so at their dc bias point (don't leave it running like that - I doubt the package can manage the dissipation: it probably gets fairly warm even at the 100mA).

    2, 4, and 16 are dummies that you can use to run the surface ground into the paddle area - 2 and 4 allow you to bring the transmission line all the way in without a discontinuity. 16 is to run a ground in alongside the vdd to improve the decoupling performance (the return current has to get across to 6). The designer is just steering you as to how they thought the layout would work.

    The paddle will be the substrate connection, which you'll probably want to heatsink with vias down to the plane. I would guess the input termination goes down to the paddle, that would seem to make most sense, but I'm not very familiar with this kind of stuff - it might go to GND at 6.

    The chip designer seems to have intended the copper under the paddle to be the common point between input and output.

    What's interesting is that the 3rd party who designed the evaluation board have done the layout in a different way, isolating the paddle on the surface layer and using the plane for everything. I would assume they know what they're doing, so it would be interesting to know the pros and cons of the two approaches.

    Disclaimer: I've never done any RF, so decide for yourself if this makes any sense. I do have vague memories of how a FET works, though (retired engineer!).