In the process of developing a new Xilinx Zynq SoC system, it's important to know the specifications of the hardware and see the timing of signals. Unfortunately, the speed of the QSPI transactions in the boot sequence isn’t always an evident specification. Digilent Digital DiscoveryDigital Discovery and High Speed Adapter High Speed Adapter system is capable of visualizing QSPI transmission which can take place at much higher clock speeds, over 100 MHz. Because of the 512 MB DDR memory that the Digital Discovery has, it can perform very large acquisitions. Then, engineers and developers can visualize the boot sequence to determine timing.
The Digital Discovery is a USB Logic Analyzer, Protocol Analyzer and Pattern Generator. The digital inputs and outputs can be connected to a circuit using simple wire probes or breadboard wires. Alternatively, the Digital Discovery High Speed Adapter and impedance-matched probes can be used to connect and utilize the inputs and outputs for more advanced project.
Driven by the free WaveForms software application, Digital Discovery can be configured to be the following instruments:
- 24-channel digital logic analyzer (1.2…3.3V CMOS, up to 800MS/s (with the High Speed Adapter))
- 16-channel pattern generator (1.2…3.3V CMOS, 100MS/s)
- 16-channel virtual digital I/O including buttons, switches, and LEDs – perfect for logic training applications
- Digital Bus Analyzers (SPI, I²C, UART, I2S, CAN, Parallel)
- A programmable power supply of 1.2…3.3V/100mA. The same voltage supplies the Logic Analyzer input buffers and the Pattern Generator input/output buffers, for keeping the logic level compatibility with the circuit under test.
We can look at the boot sequence of the flash on Digilent ZYBO Zynq SoC platform. First of all, you need to use SOIC clip to bring the QSPI signals out and feed them into Logic Analyzer of Digital Discovery.
Then, you can use javascript to create the debugging test and translate the signals into data in WaveForms. This can be done by choosing Click to Add Channels -> Custom in the Logic Analyzer.
// rgData: input, raw digital sample array
// rgValue: output, decoded data array
// rgFlag: output, decoded flag array
var c = rgData.length // c = number of raw samples
var pClock = false; // previous *** signal level
var iStart = 0; // used to keep track on word start index
var cByte = 0; // byte count per transmission
var cBits = 0; // bit counter
var bValue = 0; // value variable
var fCmd = true;
for(var i = 0; i < c; i++){ // for each sample
var s = rgData[i]; // current sample
var fSelect = 1&(s>>0); // pin0 is the select signal
var fClock = 1&(s>>1); // pin1 is the clock signal
var fData = 1&(s>>2); // pin2 is the data signal
var fData4 = 0xF&(s>>2); // DIN 2-5 DQ 0-3
if(fSelect != 0){ // select active low
// while select inactive reset our counters/variables
iStart = i+1; // select might become active with next sample
cByte = 0;
cBits = 0;
bValue = 0;
pClock = false;
fCmd = true;
continue;
}
if(pClock == 0 && fClock != 0){ // sample on clock rising edge
bValue <<= 4; // serial data bit, MSBit first
bValue |= fData4;
cBits++;
if(cBits==2){ // when got the 8th bit of the word store it
cByte++;
// store rgValue/Flag from word start index to current sample position
for(var j = iStart; j < i; j++){
// Flag change will be visible on plot even when data remains constant.
// This is useful in case we get more consecutive equal values.
rgFlag[j] = cByte;
rgValue[j] = bValue;
}
iStart = i+1; // next word might start after this sample
cBits = 0; // reset bit count for the next byte
bValue = 0; // reset value variable
}
}
pClock = fClock; // previous clock level
}
Once you turn on Digilent ZYBO, the instructions will be sent from Zynq to the flash memory. You can then visualize the boot sequence in the Logic Analyzer. The application note is available at Digilent Wiki.
