Introduction
This demo project showcases a stopwatch game designed in Verilog for the Basys 3 FPGA development board . The idea behind it is simple but effective: the user presses a button to start a timer and then tries to stop it at the perfect moment. It’s a fun, hands-on way to explore essential digital design concepts like finite state machines, counters, and basic I/O handling, all implemented using a hardware description language.
The Basys 3 is one of the best boards on the market for getting started with FPGA. It is an entry-level development board built around a Xilinx Artix-7 FPGA.
As a complete and ready-to use digital circuit development platform, it includes enough switches, LEDs, and other I/O devices to allow a large number of designs to be completed without the need for any additional hardware. There are also enough uncommitted FPGA I/O pins to allow designs to be expanded using Digilent Pmods or other custom boards and circuits, and all of this at a student-friendly price point.
What You Need
To run this project, you’ll need a Basys 3 board and a MicroUSB cable for programming. You'll also need to install Xilinx Vivado on your computer. The version you use must match the release version of the stopwatch demo files. For the most recent version of the project, Vivado 2024.1 is required. The demo package includes a ready-to-use Vivado project and a compiled bitstream file for quick deployment.
How It Works
After downloading and extracting the project files, you open the Vivado project from within the software. If the bitstream has already been generated, you can proceed directly to programming the board. Otherwise, you’ll need to go through synthesis and implementation before generating the bitstream. These processes convert the Verilog code into a format that the FPGA can use to configure its logic circuits.
Once the bitstream is ready, you connect the Basys 3 board to your computer, open Vivado’s Hardware Manager, detect the board, and program it with the bitstream. After programming, the stopwatch game begins running on the FPGA automatically.
Playing the Game
When the game starts, pressing the right-hand button (BTNR) initiates the timer. The 7-segment display starts counting, and the LEDs begin lighting up from right to left. Your goal is to press the left-hand button (BTNL) at the exact moment when all LEDs are on.
If your timing is correct, the LEDs will blink, and the 7-segment display will freeze to show your score. If you press too early or too late, the LEDs will turn off one by one, and your score will be cleared. The game resets automatically, and you can play again to improve your reaction time and precision.
Inside the Design
The stopwatch is implemented using a finite state machine and supporting logic to manage timing, input debouncing, LED animation, and display control. The Verilog code is modular and easy to follow, making it ideal for students learning how to structure digital systems. Alongside the main functionality, the project includes simulation testbenches that allow you to validate the design in Vivado’s simulator before deploying it to the board.
Why It’s Useful
This project is more than just a game—it’s a compact but complete introduction to real FPGA development. It gives you experience with writing HDL, setting up and building a Vivado project, working with constraint files, programming the board, and even running simulations. For anyone starting out in digital design or looking to solidify their understanding of FPGAs, this demo provides a practical and engaging way to learn.
Where to Find Full Instructions
If you want a detailed, step-by-step walkthrough—including file locations, build procedures, simulation setup, and programming instructions—you can find the full guide on Digilent’s website:
https://digilent.com/reference/programmable-logic/basys-3/demos/stopwatch