Genesys ZU Zmod AWG Demo

Overview

This demonstration project is designed to showcase the use of the Zmod AWG 1411  module in combination with the Genesys ZU  development board. It provides a functional starting point for anyone looking to build their own arbitrary waveform generator functionality, and it also serves as a straightforward method for verifying that the hardware setup is working as expected.

Hardware and Software Requirements

To run this demo, you’ll need either the Genesys ZU-3EG  or ZU-5EV board, a MicroUSB cable, a stable power supply, and a Zmod AWG 1411 module. On the software side, the demo requires a Vivado installation compatible with version 2024.1, as well as the classic version of Vitis. At the time this was written, Digilent did not yet support the newer Vitis Unified UI, so sticking with the classic interface is essential.

The Digilent Genesys ZU is a standalone Zynq UltraScale+ EG/EV MPSoC development board, designed to provide an ideal entry point by combining cost-effectiveness with powerful multimedia and network connectivity interfaces. There are two variants of the Genesys ZU: 3EG and 5EV. These two variants are differentiated by the MPSoC chip version and some peripherals.

Project Compatibility

As with other FPGA demos from Digilent, this one is tied to specific board variants and tool versions. Each release includes the relevant files for a particular combination of board and Vivado version. For example, a release tagged for the ZU-5EV board will only work with that version and must be run using Vivado 2024.1. Older releases used a different repository structure and tag format, so users working with legacy tools will need to reference documentation specific to those versions.

Project Files

Each release includes two key archives: a Vivado project in .xpr.zip format and a Vitis workspace in .ide.zip format. The Vivado archive contains the hardware design and can be opened and modified if needed, although this isn’t required just to run the demo. The Vitis archive, on the other hand, contains the software application that runs on the board. Unlike the Vivado files, this Vitis project archive should not be unzipped manually; Vitis imports it directly in its original form.

Running the Demo

Once everything is set up, the demo runs as a simple interactive test through a serial terminal. The application cycles through four configurations: uncalibrated outputs at low range, uncalibrated outputs at high range, calibrated outputs at low range, and calibrated outputs at high range. At each stage, a ramp waveform is generated on both AWG output channels. A newline character sent via USBUART will advance the demo to the next configuration.

By connecting an oscilloscope, such as a Digilent ADP2330, to the SMA outputs, users can measure the peak-to-peak voltage of the generated signals. The output waveforms span the full digital range of the device, offering a comprehensive check of the output range across calibration and gain settings.

Rebuilding the Project (Optional)

While running the demo requires no hardware modifications, users who want to customize or rebuild the hardware platform can do so. This involves opening the Vivado project from the release, generating a new hardware design, and exporting it as an updated platform for Vitis. The workspace structure is designed to support platform updates, including a workaround for known issues related to FSBL generation and BSP optimization.

When making these changes, users must manually replace certain initialization files and verify that paths to the FSBL ELF and XSA files are correct. The process includes rebuilding the FSBL, boot components, and the master system project, ensuring that all dependencies are properly updated after any platform changes.

Demo Output and Results

The demonstration provides clear, measurable output for each configuration, giving users a solid understanding of how the AWG performs under various settings. Sample measurements show how the output range differs before and after calibration, and how gain settings affect signal amplitude. While the test data referenced is based on a factory-calibrated module from several years prior, users can expect even more accurate results with a recently calibrated unit.

Here’s an example of the kind of data the demo can produce:

These values demonstrate how calibration significantly improves accuracy in both low and high output ranges.

Final Thoughts

This demo offers an effective and practical way to validate the Genesys ZU  with the Zmod AWG. Whether you're looking to confirm that your board is working or planning to extend the design for more complex waveform generation tasks, this project provides a strong foundation.

Additional Resources

For further reading, including HDL development guidance and workspace navigation in Vivado, you can explore Digilent’s resources on creating hardware designs. Technical support is also available through the Digilent FPGA Forum, where engineers and community members can help with troubleshooting or project customization.

If you’re looking for the full set of steps—such as importing the Vitis project, building software applications, or exporting hardware platforms—you’ll find all the detailed documentation on the official Genesys ZU Zmod AWG demo page on Digilent’s website.