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  • Author Author: Jan Cumps
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Design a PCB and follow manufacturer, data sheet and designer recommendations - part 1: collect the rules

Jan Cumps

In a recent blog, I made a pcb for a piezo sensor circuit. 
image
image: the schematic in KiCad
I used general common sense when doing the layout. I put the components and traces in such a way that they fitted and didn't have trace crossings. But I didn't follow instructions from the designer () or manufacturer (TI).
image
image: original single layer layout in KiCad
Let's redo this, and try to adhere to the layout and component choice recommendations.

Here are the ones I collected:

image
image: I collect the layout and design recommendations on the KiCad schematic

From the circuit designer paper and comments on element14

  • Care must be taken in the choice of passive components, especially C1, which should be stable and low noise. Polystyrene capacitors are capable of very good performance (types vary so careful selection and testing is required) and surface mount NPO or COG ceramics can give acceptable performance. Other ceramic types are not suitable.
  • if C1 = piezo capacity, the output is the same as the open circuit output of the sensor (gain is 1 in the -3dB range)

From the OpAmp data sheet

For best operational performance of the device, use good PCB layout practices, including:

  • Noise can propagate into analog circuitry through the power pins of the circuit as a whole, as well as the operational amplifier. Bypass capacitors are used to reduce the coupled noise by providing low impedance power sources local to the analog circuitry.
    Connect low-ESR, 0.1-μF ceramic bypass capacitors between each supply pin and ground, placed as close to the device as possible [...].
  • Separate grounding for analog and digital portions of circuitry is one of the simplest and most-effective methods of noise suppression. One or more layers on multilayer PCBs are usually devoted to ground planes. A ground plane helps distribute heat and reduces EMI noise pickup. Take care to physically separate digital and analog grounds, paying  attention to the flow of the ground current.
  • To reduce parasitic coupling, run the input traces as far away from the supply or output traces as possible. If it is not possible to keep them separate, it is much better to cross the sensitive trace perpendicular as opposed to in parallel with the noisy trace.
  • Place the external components as close to the device as possible. Keeping RF and RG close to the inverting input minimizes parasitic capacitance, as shown in Section 11.2 [I will show the image when we get at this rule]. 
  • Keep the length of input traces as short as possible. Always remember that the input traces are the most sensitive part of the circuit. 
  • Consider a driven, low-impedance guard ring around the critical traces. A guard ring can significantly reduce leakage currents from nearby traces that are at different potentials.

Additional resource:

  • Cadance blog: what is a guard ring and how to design it properly

The KiCad 6 project is attached. You can play along.

piezo_charge_circuit_20220821.zip