LOGI-PI-2 - Would this dev board allow an external clock source to be connected ?

Since it is open source, you can change the clock from the external 50 Mhz clock on the PCB if and only if you are a pro with SMT boards since this is a 4 layer board. You will void any warranty as well. But there maty be  another problem lurking in the wings.

The Raspberry Pi to FPGA main communication interface is the PI SPI port.  The Max stable SPI clock rate that has been tested is 32-48Mhz.  Based on our development experience there are some instability issues that can occur when using higher clock rates.  By default the current LOGI SPI drivers runs at 48 Mhz  With the current 48Mhz clock and direct communication to the FPGA the user can expect to get 4 MB/S throughput between the Raspberry Pi and the FPGA.
From: LOGI Pi User Manual - ValentFx Wiki

Clem

Hi Clem,

Thanks for your speedy reply !

Yes I completely understand all these concerns and have had them myself, I will be looking to remove the 50 MHz oscillator and inserting my own 100 MHz from an analog devices PLL. However just from some quick glances at the PCB, the location of the oscillator is not evident, on the schematic it is identified as component U4 though.

Additionally I do not intend on transferring a significant amount of data to the FPGA, and there will be pretty much no communication between the Pi and the FPGA other than some initial programming and parameter configurations, in other words no where close to the stated max data rate.

But if this 100 MHz will force the SPI and subsequently the Pi to operate at these speeds then I can see why issues arise. I am thinking something to divide down the frequency to the SPI bus, but if these are all internal connections I don't think it will be possible..

There is (almost certainly) no need to change the external clock - the chip has two CMTs each of which contains a PLL.  Use a PLL to up-convert the 50MHz clock to anything you fancy (and that the chip can cope with).

If you are using SPI to talk to the PI then make sure you run it at  a suitable speed.

It's very common to use several different clocks in one FPGA - one of my current  projects uses 40MHz, 100MHz, 125MHz  and 160MHz.

MK

Hi Michael,

Many thanks for your reply, my application demands that the clock for the FPGA is exactly 100 MHz as it is derived from an ultra stable atomic clock. The FPGA will provide precise timing capabilities with respect to the external clock. Just to clear things up however, does the SPI bus and the FPGA need to run on the same clock frequency, if not is it possible to inject a lower frequency clock to the SPI, but still deriving it from the 100 MHZ ?

I'm not familiar with the Logi PI board but I am with FPGAs. The FPGA you have is fully capable of  operating with multiple clocks - serious FPGAs don't have  a single clock input like micros.

You need to check on the data sheet for the FPGA which pins are suitable for clock inputs (only a few will be) and then find one which is available on your board.

At 100MHz you'll need to think very carefully about signal integrity, possibly using LVDS to connect the clock to the FPGA. If your atomic clock was able to provide a lower frequency clock it might be better to use that and PLL to the required internal clock frequency for your FPGA logic.

There is plenty of material on the Xilinx website about the FPGA and its clock handling capabilities.

Generally speaking it is a bad idea to use an external clock like the 100MHz from your atomic clock as the clock for the control functions of the FPGA since it will stop working if the external clock should stop. Much better use the on board 50MHz clock for control stuff and the 100MHz precision clock (or derivatives of it ) where needed.

MK

Hi Michael,

You are indeed correct regarding signal integrity, the 100 MHz i wish to deliver is differential LVPECL (fully programmable) to the FPGA. I am just looking at the Spartan 6 datasheet right now and can see that it does mention clock inputs in the I/O section: "I/O clocks are especially fast and serve only the localized input and output delay circuits and the I/O serializer/deserializer..."

Forgive me as I am not incredibly familiar with FPGA's but is this saying that clock injection through the I/O pins only serves the I/O and does not serve as the FPGA core clock? Or am I inferring incorrect meaning from this sentence?

The PLL has holdover capabilities so the 100 MHz becoming absent is not an incredible issue and it would be very preferable to maintain the 100 MHz local clock as it is a source to an even bigger system which does require this frequency. I do have a free PLL channel though so this is also not set in stone.

Coming back onto the issue of signal integrity would using the I/O affect the quality of the clock, delays etc? Or would it be best to figure out how to inject cleanly into the proper clock input in place of the 50MHz crystal ?

The clock on the Logi Pi board goes in to the FPGA via R13 - it is single ended.  There are some clock inputs on the SATA connector and these are differential and could be used with the external 100MHz clock if it supports suitable logic levels (the input need to be configured  and you need to understand the FPGA to do this.)

If you have  a bad clock you will have jitter and possibly missing pulses. If the clock is bad enough (and it easily can be at 100MHz) the jitter will mean that the while thing just won't work. You are unlikely to end up with a working design if you take the 100MHz in though a non clock input.

The bomb proof way to do this is to divide the 100MHz reference clock down to perhaps 10MHz , this will be much easier to get into the FPGA but use LVDS if the wires are more than a few cm long, then regenerate the 100MHz using  a PLL.

Don't worry about the on board clock - it is probably best to leave it there so that the demo software that comes with the board will work and I would suggest using it for control logic. If you don't want to use it then just ignore it.

What are you trying to do here - unless your mission is to learn about FPGAs it might be better just to buy something.

MK

Jarez Patel wrote:

 

You are indeed correct regarding signal integrity, the 100 MHz i wish to deliver is differential LVPECL (fully programmable) to the FPGA. I am just looking at the Spartan 6 datasheet right now and can see that it does mention clock inputs in the I/O section: "I/O clocks are especially fast and serve only the localized input and output delay circuits and the I/O serializer/deserializer..."

 

Forgive me as I am not incredibly familiar with FPGA's but is this saying that clock injection through the I/O pins only serves the I/O and does not serve as the FPGA core clock? Or am I inferring incorrect meaning from this sentence?

The Xilinx Spartan-6 LX9 on the Logi-Pi has many "GCLK" (global clock) inputs.  GCLK inputs can clock anything on the chip, not just I/Os.  The documentation mentions I/Os because if you use the flip-flops in I/O pads you minimize setup/hold times and clock-to-output propagation delays, which makes it easier to meet your design's timing requirements.

I have a Logi-Pi "one" and my comments refer to it, but I don't think the clocking changed from Logi-Pi "one" to "two".   You should be able to find the Logi-Pi schematics at element14 or at the ValentF(x) site.  The schematics show you which LX9 pins can be clock inputs: look for "GCLK" pin names.  Also check the Spartan-6 data sheet, which you can download from Xilinx.

You may be able to hook up differential LVPECL directly to a pair of differential pins on the LX9.  Take a look at the Xilinx Spartan-6 user guides.  You might also be able to use internal termination on the chip itself so you don't need to add any termination resistors.

The Logi-Pi has a SATA connector that is routed to two differential pairs on the LX9.  On the Logi-Pi "one" there's a SATA pair that connects to a GCLK pair.  The Logi-Pi doesn't support SATA per se, but does have the correct differential pair and ground pinout so you can use a SATA cable.

The 100 MHz clock doesn't have anything to do with SPI unless you're designing your own SPI master, in which case you'll be dividing it down to something more reasonable.  The LOGI-Pi does use SPI for downloading a bitstream from a Raspberry Pi host, but in that case the LX9 is acting as a slave and uses the pre-defined configuration pins.

Hope this helps!

Hi Michael,

This is incredibly helpful, my analog devices PLL (Clock source in this scenario) can provide either LVPECL, LVDS and CMOS at two adjustable current levels. If I am reading correctly I can insert this 100 MHz through the SATA connector which directly goes into AN clock input for the FPGA.

Alternatively I could inject a lower frequency say 10 MHz and step that up on the FPGA to 100 MHz using the PLL ??? (this could work for me as long as it is all synchronised but what is the better option?)

My application is for a precision timing distribution system, I need the FPGA to send out pulses at kHz but it needs to be aligned with the 100 MHz clock derived from the atomic clock. Additionally I need pre pulses sent ~10ns before each kHz pulse to prep a HPA.

& this is more of a task/project for me but it will also mean I will learning using FPGA's on the way. I know HDL but have never actually used an FPGA hence all this I/O configurability etc is all new to me, it is typical uni learning scenario where I understand the theory and not the application. I am more savvy to RF systems and circuits.

It's going to be quite hard to get this all to work - and gets harder the longer the distances between the FPGA and other things. If the kHz range pulses need better than 10ns synch relative to the 100MHz clock you will need to use LVDS or similar to get them along any wires. I just did a design with a remote strobe 2m away from the FPGA, I only wanted 300nS pulses with 20nS timing but we still used LVDS drivers and transceivers to get the signals in good condition at the other end of the wire. And you'll know that 2m of wire is about 10ns so you may need to consider wire length compensation in the timing of you kHz pulses.

If I were doing this I would use a dev board to get the basics right and accept that the signal integrity is rubbish and then make a board with suitable interface chips for the clocks and  pulses. If you go this route (using the LOGI PI board) you can pipe the 100MHz into the Spartan clock inputs on the SATA connector with them set up for LVDS and even experiment with running the clock direct or though the Spartan's PLL. Once you have the logic working correctly you will almost certainly need a custom pcb for the line drivers/receivers and it will all work so much better if you put the FPGA on the same board. I think the LOGI PI is open source so it should be legal to clone the bits of their design that you need but do please check the legality of this before you do it.

MK