We have a couple of these in the office that we can run software / test some things on - so what would you like to see tested on the hardware that would help to swing the decision for you as to whether or not it's worth it?
I've seen a few questions about Sega Rally running on MAME, questions about h264 encoding, realtime transcoding - for some of these I'd have to find the software/setup but it's certainly do-able.
So let me know, what do you want to see tested on the Pi 4?
Some progress in writing data from Pi to FPGA, I'm able to send packets of 2048 words (16 bits wide) in a typical time of about 175us. No errors so far but I've only sent a small number of packets.
Rate = 23.4 Mbyte/s.
Next to try and get FPGA -> Pi up to a reasonable rate.
I'm not quite as fast as PCie (
) but this works without modding the Pi !
MK
Well, I have the ability to send data packets in both directions and I don't get errors.
The sad news is that Pi Reads of the IO seem to top out at about 264ns - the code loop is very simple:
| GPIO_SET(P_FRAME); | // start the frame |
while(word < n_words)
| { | ||
| gpio_regs[7] = (1 << 18); | // set MR high | |
| //gpio_regs[7] = (1 << 18); | ||
| *data++ = gpio_regs[13]; | ||
| gpio_regs[10] = (1 << 18); | // clear MR | |
| //gpio_regs[10] = (1 << 18); | ||
| *data++ = gpio_regs[13]; | ||
| word += 2; | ||
| } |
| GPIO_CLR(P_FRAME); | // end the frame |
adding the commented out statements or changing the level of compiler optimisation make no difference at all to the speed, the MR pulses remain at 264ns and the period at 528ns.
This looks like 32 - 33 cycles of the IO clock (assuming it is 120MHz or 125MHz - I've seen both claimed.)
It would not surprise me if there is a setting in the processor that could change this - so if any RPi bods are reading this - please let me know !!
As it is I can transfer 7.575 Mbyte/s into the Pi from the FPGA. It would be so nice to go at twice that speed 
.
@ Christopher Stanton - do you have any RPi contacts you might ask ?
MK
