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What's Stopping You Building Your Next Project with an FPGA? (Please, Don't Blame the Cost!)

rscasny

The community does a ton of projects with MCUs. If they do the job for you, that's great. But the element14 community is about learning, experimenting and roadtesting. In this spirit, I am proposing that you should try building your next project with an FPGA (SoC), if it suits the application, of course. What's stopping you? Oh, some members have voiced the cost issue. Granted, some FPGAs do cost a lot. But chip manufacturers are rolling out economical chipsets that most makers, pro-makers or experienced hobbyists can afford. (If you can't, then apply to a RoadTest and if you win you can get a dev board for FREE.) I think FPGA / SoCs will move into a more important place for electronic designers, especially for IoT applications. Perhaps it's time to experiement with one. What's stopping you?

 

Here's a link to a current roadtest:Digilent ARTY S7 Dev Board (Xilinx Spartan 7)   Apply today!

 

Randall Scasny

RoadTest Program Manager

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  • A bit late to the party but I'd have to say that I've not had many projects actually need the capabilities of an FPGA. Even when they do, having to think differently and either do schematic capture or VHDL/Verilog programming takes a bit of practice after being of the "procedural" mindset for microcontrollers and the likes.

     

    But I think the biggest annoyance from when I was tinkering with FPGAs was the toolchain. Xilinx ISE Webpack was a mighty large download that consumed close to half of my boot SSD, ran slowly, took a decent amount of time to synthesize and build a bitstream and wasn't very beginner friendly when it came down to the subtleties of FPGA designs. For example, warnings about maximum clock rates on a net, or clock-skew warnings, errors about clock sources coming in from less than desirable pins (due to the design of the prototyping board) which, while useful, don't exactly give us that much insight into how one might work around the limitations of a particular FPGA product. It was great that it was free, but I just wished it could be a little more friendly, lean and optimized. Some of the nice features like a graphic simulation (if I recall correctly) have been removed in later versions which was a shame. The limitations of Webpack were not the best either - as some Digilent prototype boards can accommodate designs which are on the borderline of what is allowed (e.g. if trying to integrate a soft-core from free HDL sources) - and WebTalk being not-disableable in later versions means Xilinx basically gets metadata about every generated design (which I don't like).

     

    - Gough

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  • A bit late to the party but I'd have to say that I've not had many projects actually need the capabilities of an FPGA. Even when they do, having to think differently and either do schematic capture or VHDL/Verilog programming takes a bit of practice after being of the "procedural" mindset for microcontrollers and the likes.

     

    But I think the biggest annoyance from when I was tinkering with FPGAs was the toolchain. Xilinx ISE Webpack was a mighty large download that consumed close to half of my boot SSD, ran slowly, took a decent amount of time to synthesize and build a bitstream and wasn't very beginner friendly when it came down to the subtleties of FPGA designs. For example, warnings about maximum clock rates on a net, or clock-skew warnings, errors about clock sources coming in from less than desirable pins (due to the design of the prototyping board) which, while useful, don't exactly give us that much insight into how one might work around the limitations of a particular FPGA product. It was great that it was free, but I just wished it could be a little more friendly, lean and optimized. Some of the nice features like a graphic simulation (if I recall correctly) have been removed in later versions which was a shame. The limitations of Webpack were not the best either - as some Digilent prototype boards can accommodate designs which are on the borderline of what is allowed (e.g. if trying to integrate a soft-core from free HDL sources) - and WebTalk being not-disableable in later versions means Xilinx basically gets metadata about every generated design (which I don't like).

     

    - Gough

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