Digilent ARTY Z7 Dev Board - Review

Table of contents

RoadTest: Digilent ARTY Z7 Dev Board

Author: alvieboy

Creation date:

Evaluation Type: Development Boards & Tools

Did you receive all parts the manufacturer stated would be included in the package?: True

What other parts do you consider comparable to this product?: Parallella

What were the biggest problems encountered?: Lack of layout diagrams, designs are for old versions of Vivado suite/Petalinux.

Detailed Review:


I was born in 1975. And according to multiple sources, it all started in 1975. On this year, Signetics and Intersil introduced two integrated circuits, the 82S100 and IM5200, respectively. These IC were called FPLA – Field Programmable Logic Array, and they eventually evolved to what we know today as CPLD (Complex Programmable Logic Array) and FPGA (Field Programmable Gate Array). In the mean term, other devices with similar purpose existed, such as PLD (Programmable Logic Device) and GAL (Gate Array Logic).


The FPGA themselves have improved over time, with more resources, better (faster and lower-power) architectures. Often a soft-core CPU was implemented in FPGA, or placed side by side, because some workloads are more easily managed by a CPU than by pure logic.


Then back in 2011 Xilinx introduced a new type of device – one that merges CPU (a dual-core ARM Cortex-A9) and FPGA fabric into a single chip die – the Zynq 7000 series. Altera followed the trend by launching Cyclone V the very next year. These new devices bridged the gap between the CPU and the programmable logic, leading to very fast interconnects and a level of integration never seen before.


In 2012 Digilent introduced one of the first Zynq-based evaluation boards to the market targeting starter engineers, hobbyists and academics – The Zedboard. Other boards then appeared on the market (from Digilent), such as Zybo-Z7, Pynq-Z1, Cora-Z7 and the board under scrutiny here, the Arty-Z7 (-20 variant).


First impressions

The board arrived well-packed, in a very small paper case where one could find the board and some protection plastic. After opening the box, one thing was clear, though - there were no cables at all, nor a power supply. According to the documentation, the board can be powered by either USB or by using an external DC adaptor (9V to 15V), requiring one to change a jumper in case you are not interested in the default power option (which is external power supply).

At the heart of this Arty Z7 20, you can find the Xilinx FPGA SoC: The Zynq XC7Z020. It features the dual-core ARM, as well as 53,200 LUT, 106,400 Flip Flops, almost 5Mb of internal block RAM (~600KByte), more than 200 DSP slices. Juicy.

It was also clear from the documentation that I’d need an SD card – my plan was to run a Petalinux distribution of considerable size, and the board lacks an eMMC, and probably won’t be feasible to place the system on the QSPI flash. Luckly I had a spare SD card around, so no problem on that side.

The design

The programmable logic (PL) on Zynq devices can be implemented using the Xilinx Vivado suite. For this roadtest I have used Vivado v2017.3, which I had already installed previously for other projects. Note that you will have to import the board design files into Vivado prior to use any pre-built design for Arty.


For this roadtest I decided to use a freshly-developed RGB panel controller I wrote in VHDL. Although not intended for Zynq devices, the only changes required was to migrate from the Wishbone bus I use on my projects to the AXI and AXI-Lite buses required for Zynq.


Instead of starting from scratch, I have based my design on Digilent’s linux_bd design, which you can find here: https://github.com/Digilent/Arty-Z7 .

So after rewriting the bus part of the RGB controller, and adding it to the Vivado project, all I had to do was to run the connection automation and connect a few other missing wires (such as reset), as well as picking a new clock from the PS core (I need 64Mhz for the RGB clock). I also had to remove two GPIO controllers, the ones accessing the headers on the Arty board, because I will need to use those to drive the panels (through a shield board, we’ll come to it).


Here's the full design as seen in Vivado. You can see the RGB controller on the top-right of the screen.

A full view of the design:

Here's a closer view of the RGB contoller.

A view of the IO constraints for the design, where the RGB signals are mapped to FPGA pins and therefore to the shield headers.

The software

Only the braves mess with Petalinux. Luckly enough, I had previous experience with Petalinux so only a minor amount of bravery was needed to get things working on this board.

The design was based on the Petalinux files available here: https://github.com/Digilent/Petalinux-Arty-Z7-20 .

The initial plan was to use the v2017.4-1 as tagged in that repository, but soon enough I realised it was not complete. Attempts to use any of the other tags with my installed Petalinux 2018.1 failed after me losing quite some time.


So, first thing was I had to downgrade Petalinux to an older 2017.2 version.


And it sort of worked.


I require two things for my tests and demonstration. Plan was to create a linux kernel driver for my RGB controller and expose the framebuffer as a linux “fbdev”. Second one was to install a media player suitable for playing anything on the said framebuffer. At first I tried “mplayer”, but although there are some recipes in OpenEmbedded for it, they seem not to work with Petalinux/Yocto – I actually lost quite some time with this one too.

I then decided to try “vlc”. It also did not show up in Petalinux config, but I was able to add it and since it already shipped with Petalinux it seemed to work.


Adding the kernel driver was the easiest part of this, and not hard to develop for me because I already did something similar before for ZPUino uClinux.


The shield


In order to connect the Arty to the RGB panels I decided a shield would be needed. This would ease connections since I no longer needed patch cables, and improve robustness by adding 3.3V to 5V buffers, because the panels run at 5V, and although they do work with 3.3V, the noise susceptibility is much higher.

After googling quite a bit in search for the Arty layout, or for what it’s worth, the so-called ChipKIT connector layout, and founding nothing useful (might be me…) I had to rely on some hand measurements to figure out the distance of the connectors, pitches, so on. I then moved to design the shield board and produce it, as well as ordering the components I was missing.


And I failed, hard.


When I assembled the board and went to plug it into Arty, it did not plug at all:

  • I miscalculated the analogue header (J1) size, and placed a 5x2 instead of the correct 6x2. Although the design does not use any signal from J1, this had the nasty side-effect of me placing the J7 mating connector off by 100mils. I needed power from J7, so this by itself invalidates the design.
  • I miscalculated the distance between J4 and J2/J3 – I must have assumed they would be spaced (pin-wise) by 200 mils, as it’s common on Arduino boards, and it’s also the spacing between J1 and J7, but in fact the distance between those is a rather uncommon 150mils – for you to understand how odd this is, imagine those were male headers and you were to connect a breadboard to them – one of the connectors would not mate with the breadboard at all.


Here’s what happens if I place a breadboard side-by-side with J4 and J2/J3: if I align the breadboard holes with J4, the misalignment on J2/J3 is clearly visible, and equals 50mils (half regular spacing between holes).

So, this rendered the “v1” board useless. I had to order a new one, but unfortunately did not arrive in time for this roadtest (but I plan to update it once it does).


Running everything


Booting the Arty with the newly-build Petalinux was quite easy, once I knew all the required details:


Booting into Petalinux

Booting via SD card.

The final setup

Let me talk you a bit about the RGB panel. It’s a “massive” panel, built with standard HUB75 32x32 panels, on a matrix 5 by 4, totalling 160 pixels by 128 pixels. Looks not very much, but here is it, with the “v1” shield connected and Arty board side by side. Also a size comparison with Arty itself.

Unfortunately I had not the time to test this beast, but I plan to do it on the upcoming days, using jumper cables as you can see attached to the shield board. Probably I’ll have to do some fixing on the VHDL too.




The Arty-Z7 is a nice board. It includes a massive FPGA and the dual-core CPU that runs Linux natively.

The pros:

  • Big FPGA, for large projects
  • Looks well designed and robust.
  • Handful of IO’s on headers and the PMODs
  • FTDI-based design helps with serial output and debugging (not tested)

The cons:

  • A bit pricey – you can get a Pynq for much less money and it probably suits your needs
  • Lack of documentation (layouts, how-tos) and more complex examples.
  • No SD card, no cables, no power supply.

All my design files will be available on https://github.com/alvieboy/Arty-Z7-RoadTest

  • Thanks Gene. Stay tuned. Will probably take two weeks or so for the new boards to arrive, and I'll update you guys then.


  • Hi David. Yes, that's what I did yesterday - use some jumper wires, but I hit some other major issue which needs resolving (see my answer to Rod for some details).

    I'll keep you guys posted once I get the electronic part to work.



  • Thanks for your feedback Rod. Regarding the panel, I am afraid I'll have to wait for the "v2" board, which I had to redisign a bit. Revision 1, in addition to the layout problems I already explained, has another major issue - noise (lots!) on the colunm selector lines. This is due to the fact I chose a bi-directional buffer (TXS0104E) for those lines, cause all I needed was 4 extra buffers, and was not to waste another 16-bit buffer. Note to self - never again use bi-directional buffers for uni-directional stuff.
    Here's a capture of some signals on the HUB75 (panel) connector. The COL lines should be steady at '1' and '0', but seems that instead of going to '0' they oscillate.

    This will not happen on V2 board, cause I used another 16-bit buffer (and buffered the lines independently).

    I'll post some news once board arrives.


  • Very nice roadtest review.  I enjoyed the brief history of Field Programmable Logic Arrays.  What an exciting time.

    It will be interesting to see your finished project.

    Good luck,


  • A nice review. I can see you put some work into this. A shame that a small alignment mistake caused problems. (We all make mistakes, but why we're still burdened with that original Arduino one is a mystery.) Was there no way to kludge it with a few ugly jumper wires?


    I'm looking forward to seeing how rev 2.0 of the board works.

  • Hi Alvaro,


    Very interesting review, which I need to go through in a bit more detail, but I like the way you've jumped straight into the detailed Zynq processor and Petalinux. I'd love to see you light that panel up (would definately be worthy of a 'Exceptional' rating )