Evaluation Type: Evaluation Boards
Did you receive all parts the manufacturer stated would be included in the package?: True
What other parts do you consider comparable to this product?: null
What were the biggest problems encountered?: The drivers are not signed, hence fail to install on windows 10. The solution is to boot windows in a mode that does not enforce driver signatures and then manually install the driver.
Recently I was doing a few Analog/RF projects and needed a high dynamic range ADC to digitise various outputs, so being given a chance to review this was very exciting. The evaluation board arrived with no problems and everything required to get the board up and running was included (USB cable, the board it self, a guidance brochure etc).
So I began by plugging in the supplied USB to the computer and proceeded to install the required software. This evaluation board basically needs 3 piece of software to get it going, the evaluation software package: this is the application that lets you control all the on board registers and request data from the ADC and check a few performance parameters etc, next comes the the hardware package: this is the software that contains all the info for your particular ADC IC and finally the device driver for the USB chipset on the evaluation board. The former two installed easily, but the third piece of software, the driver, was extremely painful to install. The supplied driver in the application is not signed (or at least not signed enough for windows 10) and hence fails to install. The only way around this is to boot windows 10 in developer mode, disable the driver signature checking and proceed to install manually. Despite this minor inconvenience, everything works well after this. For anyone struggling with driver installation follow: Windows 10: Disable Signed Driver Enforcement
Now lets turn to the actual software, which is quite basic and consists mainly of 2 main windows. One window allows you to set and inspect the various register bits corresponding to sample rate and filter bandwidth; you can read what the registers are currently set to, and the software gives you some nice drop down options to select the OSR, Filter and Resolution modes, which results in a corresponding sampling rate. Unfortunately, it does not tell you the exact sampling rate you end up with! For that, you must refer to the detailed tables on the datasheet. You can also measure the resultant samplying rate by hooking up a frequency counter to the interrupt pin of the ADC. If your not a fan of GUI's this chip has an excellent feature where most of the bits that you can fiddle with using the software can actually be set in hardware by tieing the relevant pins to the required power line. This is a excellent feature, because given the high data output rate of the ADC (512KSPS! on the highest setting) you will most likely interface it to an FPGA that would buffer/analyse and provide it to an MCU. Having to configure the ADC first using the FPGA would be a slight hindrance. The evaluation board even has a bank of dip switches on the PCB if you wish to set them in hardware.
Next lets talk about the data viewing/analysis window, and this is where the software is really disappointing. Before we dig into the details lets quickly talk about where this ADC could be used. Traditionally, delta sigma ADCs have been confined to very low frequencies, generally from DC to Audio. Over the years we have seen faster and faster ADC's which increase the usable bandwidth. This ADC manages excellent dynamic range upto a maximum pass band of 220 kHz! So clearly this could used for modest AC applications such as sampling a narrow band-limited signal. Hence, the important parameters of interest are the AC specs and the usual to the DC specs. Unfortunately, this where Texas Instruments does something completely unheard of and does not include a frequency domain view of the sampled data! At first I thought I just couldnt find it, but inspecting the user manuals confirmed my fears. Thankfully, TI has clearly recognised this anomaly and mentions in the manual that they are working on an FFT view for the software. I find it very surprising that an ADC evaluation software even made it through its first release without a frequency domain view. If you are interested in measuring some key AC performance spec such as SNR, THD etc you cannot do so with the supplied software, instead you can either export the data and manually process it in something like MATLAB. However, it must be noted that the datasheet obviously already contains a multitude of AC specs and FFT snapshots at various settings.
I have attached a few screenshots of all the available data analysis options, which are sparse to say the least. You can see the software compute the ADCs DC specifications such as the ENOB and the NFB. These specifications are obviously incomplete as they dont tell you how the ADC performs with an AC input.
All of the above data was acquired at the highest available sampling rate of 500 kHz! If you probe the Data Ready pin, you can actually verify it!
Lastly, perhaps a somewhat petty point, but I've noticed with the latest version of the software has unreasonably high CPU usage even during idle use.
Now lets turn our attention to the actual board itself. As you'd expect every thing is laid out very well, inspecting the BOM reveals top notch miscellaneous IC's and passives. The board has a a lot of adjustable headers and comes with all the jumpers you will need to switch to the various configurations. All the major pins (SPI, Frame etc) have been broken out to headers so you can hook up a logic analyser if you wish to do so for debugging. Furthermore, the supplied MCU can be completely decoupled from the ADC and a custom acquisition system can be connected to the board. Beware, that you would need a really top notch CPU or ideally some kind of FPGA to handle the high data rate.
Apart from the ADC, the other important IC on the board is the differential input amplifier to interface between the BNCs and the ADC. This is mainly required because of the ADC's rather high but typical nominal ZIn of 5k. Out of the box this front end has been set up as having a differential input with a screw terminal or BNC to connect to. This can be easily changed to a pseudo-single ended by shorting one of the jumpers to ground. Systematically speaking, the left side of the board has a differential ADC driver, followed by the ADC itself and finally a beefy CPU to handle acquisition. The sampled data is buffered and sent over a fast USB 2.0 chipset to the PC. All in all, the circuit layout has been almost completely been religiously copied from the datasheet which is excellent.
Unfortunately, the same praise cannot be extended to the clock arrangement of the CPU and ADC, it seems warnings from the datasheet have been completely ignored! The ADC is clocked using a 16 MHz oscillator that have been divided by 2 and 4 to give a choice of 8 Mhz and 4MHz. The CPU on the other hand has been supplied with its own 16 MHz clock. These two clocks are not phase locked (or are not, simply the same!) hence can potentially intermodulate eachother. Consider the 2 clocks labelled 16MHz with a slight frequency (or phase) deviation between them, now imagine the CPU clock somehow gets capacitively coupled onto the ADCs clock perhaps through the SPI master clock; As a result the ADC is going to see a linear combination of the two clock sources as its own clock source i.e A*CLKadc + B*CLKcpu. Now if we recall that the Delta sigma ADC or any ADC for the purpose of analysis is non linear and behaves like a mixer, we can expect the difference frequency (and sum) between the two clock and its harmonics to clutter the already precious passband. This is even more damning for an ADC designed specifically to be used to digitise DC or thereabouts with high dynamic range. Although I greatly exaggerate this phenomenon and add that the crystals are routed well apart from each other this is simply something that does not instil confidence. On the bright side, TI acknowledges this error on the evaluation boards datasheet and promises that any additional spurs seen beyond the specification are not due to the ADC but rather due to the clock arrangement. For hobbyist or educational uses, this assurance and the figures in the datasheet are satisfactory but someone interested in verifying absolute cut throat specs using this evaluation board, might think otherwise.
To test the board, i first shorted out jumper R70 to configure the front end for single ended input and used my Marconi Signal Generator.
Here is a 10 kHz, 0 dBm sine wave. You can see the ADC has an internal DC offset, that would need to be corrected in software.
Here is a 100 kHz, 0 dBm sine wave. It looks terrible on the plot because the input frequency is a considerable fraction of the sampling frequency leading to a small number of samples per cycle. This leads to large errors in the basic linear interpolation algorithm the evaluation software uses to join up the points. I have also manually exported the data out to MATLAB and performed the FFT with a hanning window applied.
Here is another test that really brings out the terrific dynamic range we have at our disposal. While viewing the sampled data of the board with nothing connected, I saw a somewhat periodic signal. Measuring the period of the signal reveals it is very close to 60 Hz! The front end was picking up the mains hum from my noisy lights! The signal is pretty minuscule and seems to only be peaking at 200 uV!
Whilst looking for the documentation for this board, I found out that TI has actually already released a newer revision of the PCB, clearly to rectify the issue with the clock scheme. I would strongly recommend keeping a close eye on the version you are purchasing, make sure you get the latest one! I have inspected the schematic of the newer version, and apart from the paragraph on the bad clock scheme, this review should still be relevant!
My main intention for this board was to use it with a DIY spectrum analyser I am designing. I intend to use this board to digitize the output of the final Log detector and experiment with some undersamplying scenarios. Unfortunately, the front end is still under construction so keep an eye out for updates to this review! Lastly, If anyone would like to see me conduct additional tests, I would be happy to do so!