RoadTest: HELLO FPGA Kit
Author: amgalbu
Creation date:
Evaluation Type: Independent Products
Did you receive all parts the manufacturer stated would be included in the package?: True
What other parts do you consider comparable to this product?: In terms of support for the Arduino platform, this kit is comparable with Arduino MKR Vidor board (https://store.arduino.cc/arduino-mkr-vidor-4000). It could be also be compared to evaluation boards from other manufacturers, like Intel (formerly Altera) (https://www.newark.com/terasic-technologies/p0082/cyclone-iv-e22f17c6n-fpga-de0/dp/78T4479) or Xilinx (https://www.newark.com/xilinx/dk-k7-embd-g/embedded-kit-kintex-7-fpga/dp/32AC9656?st=xilinx%20fpga)
What were the biggest problems encountered?: The biggest problem in this roadtest is that there are no projects or tutorials specifically designed for this evaluation kit. I think this is because the kit has been released recently and this is going to get better in the future
Detailed Review:
The content of the box is quite minimal: just the assembled evaluation kit, made up of three different boards and a USB cable.
The three boards of the evaluation kit look well designed and engineered. The three boards are difficult to separate, so I will try this after the roadtest in order not to make any damage to the kit, This image provides an overview of the three-bards layout
At the front, there is an LCD display by Ilitek. According to the specs, the resolution is 480x320
The middle board includes all the active components, namely the SmartFusion2 FPGA and a PIC32 microcontroller.
The SmartFusion2 housed on the board is a M2S010-1VF256, which means it provides 10K Logical Elements (LEs) for your FPGA design. This SmartFusion2 SoC also includes a 166Hz Cortex M3 processor, including ETM and instruction cache with on-chip eSRAM and eNVM and a complete Microcontroller Subsystem (MSS) with many peripherals, including CAN, TSE, USB, UART, SPI, I2C.
The external PIC32 MCU runs a C application to program PFGA, measure power consumption and communicate via USB to the provided Hello_FPGA_GUI application. Finally, the onboard memory devices include a 8 GB DDR3 RAM and an 8 MB SPI Flash used to store bootup images.
It can eventually be programmed by connecting a standard ICD3 programmer to the typical 6-pins connector. According to the schematics available here, the PIC32 is connected to the SmartFusion2 through 3 interfaces: SPI, I2C and UART. Also, two LEDs (identified as LD4 and LD5) on the PCB are connected to the PIC32, thus making them usable for a user application
The boards features many connectors, as shown in picture below
I was very excited when I read the brochure: it was claiming that there is an Arduino compatible interface. It would be great to be able to connect the HelloFPGA evaluation board to Arduino boards. As a matter of fact, "ArduinoUNO" is etched on the PCB, however there are no examples available so, if you want to use an Arduino board with the SmartFusion2 FPGA, you will probably have to implement Arduino connectivity from scratch. This may include creating you own design to route SPI, I2C or GPIOs to the proper SmartFusion2's pins and implement the communication logic in the Cortex M3 processor. In my opinion, it would have been of great help to have a reference design that implements the basic Arduino connectivity (through SPI or I2C for example) to use as a starting point for your pojects
The third board is camera board, that employs a camera sensor from OmniVision and supports resolutions of up to 640px480p in the RGB 5-6-5 format. The camera board also features a Mikrobus-compatible connector
Before proceeding, it worth to spend some time to list some of the features of the SmartFusion2 FPGA. At this link, there is a block diagram with all the components that make up this SoC
As I already mentioned, the SmartFusion 2 FPGA SoCs on the HelloFPGA Kit is a flash-based FPGA device that packs in 12,000 logic elements, 21 18K LSRAM blocks, 22, 1K µSRAM blocks, 22 math blocks that can be cascaded for DSP functions, and 2 programmable logic libraries and clock conditioning circuits. But that’s not all. The SmartFusion 2 SoC also integrates an Arm Cortex-M3 that clocks in at 166 MHz and includes a memory protection unit and embedded trace macrocell to let developers reconstruct program execution during debug. The -M3 is accompanied by a complete microcontroller subsystem, which provides instruction cache, embedded Non-Volatile Memory, embedded SRAM, and CAN, triple-speed Ethernet, USB connectivity is supported.
Very impressive, considered the cost of the kit!
The kit comes with a GUI application that guides you through the available demos. The application is available here
The zip file includes a setup that installs the FPGA GUI application in an application of your choice. The application has been developed in Java, which is good since the installation is a mere file copy and is not going to touch "sensible" system (Windows, in my case) components.
When the setup has finished to copy the files to the selected installation folder, you can launch the Hello_FPGA_GUI.exe file
Connect the board the board and you should see a serial port in the combo box in the upper-right corner of the dialog. Click the red button just on the right of the combo box: the button will switch to green and you are connected to the board.
Three demo are provided, and I will through the three of them in next sections. To run a demo you just have to browse for the dat file, select PROGRAM in the Action combo box and click the RUN button
The FIR filters demo allows to the configure a filter (low-pass, high-pass, band-pass or band-reject) and check its performances against an input signal simulated by the FPGA itself. The simulation signal is generated by getting two user-selected frequencies. The Hello_FPGA_GUI shows the input signal, the filtered signals, the FFT of the input signal and the output of the filter. If you have a look at the implementation of this demo (we will talk about development tools later), you can see that the platform provides a ready-to-use core that implements a configurable FIR filter. This is very handy for all the filtering and control application you may have in mind
The Hello_FPGA_GUI shows also the current power consumption of the SmartFusion2 SoC and can trigger the Flash*Freeze mode.
Flash*Freeze technology enables a big reduction in power consumption by stopping and starting of the FPGA fabric and related I/Os while preserving the state of the FPGA fabric. The time to either enter or exit Flash*Freeze mode is approximately 13 us. This mechanism is perfectly suited for systems that performs periodic tasks or that reacts to external events. Flash*Freeze also puts the ARM Cortex-M3 in low power modes.
Exiting Flash*Freeze mode can be initiated through I/Os or through the Cortex-M3 processor. These methods send a message to the system controller to begin Flash*Freeze exit. Using I/Os to trigger Flash*Freeze exit can be done with Signature mode or Activity mode settings.
In Signature mode, a selected set of I/Os is configured as inputs with predetermined 1 and 0 comparison states. When the input signals for all the Signature mode I/Os match their predetermined 1 and 0 states, the system will initiate Flash*Freeze exit. All I/Os in Signature mode are compared as a single signature. In Activity mode, a selected set of I/Os are configured as inputs and any change on any of the inputs will initiate Flash*Freeze exit. The device can be also have a combination of one group of Signature mode inputs and a set of Activity mode inputs, either of which can initiate Flash*Freeze exit. The Cortex-M3 processor can initiate Flash*Freeze exit through a communication to the system controller through the comm port.
In all the demos, entering Flash*Freeze mode reduces the power consumption to 0.03 - 0.04 W with a current of 35 mA, which is not a great result if compared to other low-power solution but, as far as I known, is something unique on the FPGA scene
The LCD demo displays the camera output on the display. The user can change contrast, brightness and color balance through the Hello_FPGA_GUI and the FPGA will perform all the image processing in real time
The most appealing demo is the CNN (Convolutional Neural Network) demo. In this demo, the SmartFusion2 gets frames from the camera, and looks for hand-written digits. If a digit is correctly detected, it is shown on the display and sent to the Hello_FPGA_GUI. Here is a video that shows hw the demo works
The design for this demo is a bit more complicated
The data comes in from the camera to the line_write_read block. The block performs several tasks, namely
The TOP_CNN block expects a 28x28 pixel image and processes the image according to the pipeline below
The network implemented in the demo contains 4 convolution layers, a max pool layer, and a fully connected layer. The network is trained from the standard MNIST handwritten digit database which contains the digits in 28x28 resolution images. The CNN can detect a single digit in the 28x28 image when the aspect ratio of the digit is approximately equal to the aspect ratio of the trained image data set. The network is built for only 10 classes for digits from 0 to 9 and does not use a class that shows no digit. Hence even though the camera is not pointing to a digit, the network will still output a digit that has the maximum value from thefully connected layer.
The output of the CNN is sent out to the extern PIC32 microcontroller through the UART interface. The PIC32, in turn, sends the recognized digit to the Hello_FPGA_GUI
To go deeper in the CNN example, I downloaded the development tools from the MicroSemi website. To create the FPGA design, Libero SOC is the best option. The tool can be downloaded from this link
https://www.microsemi.com/product-directory/design-resources/1750-libero-soc#downloads
During the setup process, you are asked for a license and you are redirected to the Microsemi web site in order to create a new account and generate a new license. For evaluation purposes, you can select a free licence that expires in one year. For personal use, Microsemi has the Silver licence, which allows you to use for free the SmartFusion2 with up to 25K Logic elements
Libero SoC can be launched by looking for "Libero SoC" in the Windows' start menu.
The Libero design of the AI demo can be downloaded from https://www.microsemi.com/document-portal/doc_download/1244694-hello-fpga-digit-recognition-ai-programming-and-libero-design
You need to unzip the zip file, and then unzip (with 7z) the file HF10_CNN_CAM.7z. You can now open the project file in HF10_CNN_CAM\HF10_CNN_CAM.prjx. You will be asked to update the core components, which I did
You can now have a look at the SmartDesign view of the FPGA design in the Design Hierarchy tab
So, this is something that has many components and is definitely out of my reach... For sure, the base block of the demo is an IPCore call conv_3x3. There are three layers, each one instantiating a convulotional object.
After digging a little bit in the digit recognition demo, I tried to create a very simple project in order to understand how the FPGA interfaces with the Cortex M3
I discovered that Cortex M3 can interact with the FPGA fabric through a block names Fabric Interface Controller (or FIC for short). A SmartFusion2 device has two fabric interface controllers (FIC_0 and FIC_1) as a part of the Microcontroller Sub System (MSS). These FIC blocks provide a means of interfacing from the SmartFusion2 MSS AHB-Lite (AHBL) bus to user masters or user slaves in the FPGA fabric. Each FIC block performs an AHBL to AHBL or AHBL to APB3 bridging function between the AHB Bus Matrix and AHBL or APB3 bus in the FPGA fabric. Each FIC block provides two bus interfaces between the MSS and FPGA fabric. The first one is mastered by the MSS and has slaves in the FPGA fabric; the second one has a master in the fabric and slaves in the MSS. The bus interfaces to the FPGA fabric can be either 32-bit AHBL or 32-bit APB type. The FIC block provides registered bridging between the MSS AHBL interface and the FPGA fabric AHBL/APB circuitry to run at frequency ratios of 1:1, 2:1, 4:1, 8:1, 16:1, or 32:1. In AHB-Lite configuration, a bypass mode is provided, in which signals to and from the fabric are not registered and hence requires fewer clock cycles to complete each transaction. SmartFusion2 FIC has six memory regions. You can allocate a memory region to a particular FIC that is either to FIC_0 or FIC_1. Each memory region has a predefined memory map.
More information about MSS can be found in this document.
I found a tutorial about this topic at this link
The flow to create an FPGA design and to generate the framework for the M3 application is
Unfortunately the source code attached to this tutorial available uses the M2S090TS die, which is not available for the Silver licensing plan I activated. For this reason, the project failed to load. I had to go through the tutorial steps, which, in any case, was very useful to understand how the tools work. The tutorial refers to a different Libero version (11.7 instead of 12.5), but differences were minimal I was able to complete the tutorial with no hassle. I just had one doubt when I was asked to select the correct SmartFusion2 device, but a quick look at the schematics solved the problem (see screenshot)
I had also to change something in the UART configuration, as shown below
In general, I used the settings for the "StarterKit". The resulting project is attached to this roadtest, just in case someone may find it useful.
There are two features I really appreciated in the Libero SoC suite: System builder and SartDesign
System Builder is a graphical design wizard designed specifically for SmartFusion2 based systems. System Builder takes you through the following steps:
• Selecting the Device Features for your system
• Adding any additional needed peripherals in the fabric
• Setting required configuration options for each selected feature
• Building a correct-by-design complete system
Here is an example of the steps System builder wizard
SmartDesign uses a block diagram approach for the visualization, instantiation and connection of the design. The program guides you to add and configure objects in the design ‘canvas’. Connections are made either automatically or manually via a simple point-and-click approach. The final result is a design-rule-checked and automatically abstracted synthesis-ready HDL file. The output can then be used by the standard Libero flow, all the way from Synthesis to Device programming. The diagrams in this roadtest are created with SmartDesign
Unfortunately I wasn't able to find a procedure to download the bitstream from the Libero SoC Suite. The only way was to export the bitstream into a dat file and download it using the Hello_FPGA_GUI application... not a user-friendly experience!
SoftConsole is an Eclipse-based IDE for editing, building and deploying applications to the SmartFusion2's Cortex M3 processor. In SoftConsole, you can write your own C code that will be run on the Cortex M3 processor which is integrated in the SmartFusion2 FPGA. Getting started with the SoftConsole is not so easy... I finally found this tutorial that helped me to create a SoftConsole application I was able to build. The final hurdle was the compiler complaining about a missing include file (cpu_types.h). I located the file in of the SoftConsole's fodlers Microchip\SoftConsole-v6.4\extras\workspace.examples\smartfusion2-cortex-m3-blinky\hal\CortexM3\GNU\). As a quick-and-dirty solution, I just copied the file into the root folder of the source code tree and adjusted the include paths in the compiler settings. With these changes, I was finally able to build my first SmartFusion2 application
This is absolutely an high-quality evaluation kit. It provides really a lot of computing power and additional features (like the LCD display) for a really competitive price.
