The Qorivva MPC564xL family of 32-bit Power Architecture
MCUs is designed to specifically address the requirements of the safety standards IEC61508 (SIL3) and ISO26262 (ASIL-D). It reduces design complexity and component count by putting key functional safety features on a single chip with a dual-core, dual-issue architecture, which can be statically switched between lockstep mode (redundant processing and calculations) to decoupled parallel mode (independent core operation). Qorivva MPC564xL MCUs are SafeAssure functional safety solutions.
Features
- Dual e200 Z4 CPU architecture
- Dual processing spheres including; CPU, DMA, interrupt controller, crossbar and MPU for logic level fault detection
- Two statically configurable modes of operation: Lockstep operation (redundant processing and calculations) and dual parallel mode (independant core operation)
- Fault collection unit, which monitors and manages fault events
- Error correction coding on RAM and flash memory allows detection/correction of memory errors
- Designed to address safety requirements outlined in IEC61508 and ISO26262
- Robust communications with FlexRay
and CAN/safety port high-speed low latency messaging - Cross-triggering unit coordinates ADC, timer and PWM generation and minimizes CPU interrupt load
- eTimer x 3
- ADC x 2