Rear-seat entertainment (RSE) is one of the emerging areas where programmable logic devices (PLDs) have been widely adopted. Similar to navigation systems, rear-seat entertainment systems involve a significant amount of graphics processing, especially as it relates to video quality. Figure 1 shows a typical current rear-seat entertainment system. The key components are the microcontroller (µC), FPGA, memory, other ASSPs, and peripherals. The µC is typically 16 or 32 bits. The ASSPs usually include functionalities such as decoding and controller area network (CAN) transceivers.
Figure 1. Current RSE Implementation (EP2C5 Device)
ADC = analog-to-digital converter
Next-generation rear-seat entertainment systems look quite different from the current ones. Designers are being forced to lower their bill of materials (BOMs) cost and look for ways to make the system more flexible, where they can target high-range, mid-range, and low-range platforms. One way to achieve this is by integrating some of the ASSP functionalities onto the existing FPGA. As shown in Figure 2, the µC functionality is absorbed by the FPGA (in this case, provided by Altera’s 32-bit Nios II RISC processor with a Cyclone series FPGA). The CAN interface can easily be supported within the FPGA. In addition to the CAN interface, the FPGA supports the media oriented system transport (MOST) Media LB interface. MOST is the next-generation, optical-based interface that is being widely adopted for next-generation infotainment and communication systems. For areas where MOST does not make sense, FireWire offers a viable option.
Figure 2. Next-Generation Rear-Seat Entertainment Implementation
In addition to absorbing the ASSP functionalities, FPGAs have an ample amount of room to perform video processing. With an on-chip MOST or FireWire interface, FPGAs can easily support digital video mode, giving system suppliers added feature differentiation from the competition. This system integration not only lowers the overall system cost, but also provides system suppliers more flexibility to add additional functionalities.
Altera invests significantly in the graphics area and continues to push the FPGA boundaries in the infotainment area. Figure 3 shows a dual video-in implementation of an RSE application. This dual video-in implementation can support both single- and dual-screen outputs (see A Flexible Architecture to Drive Sharp Two-Way Viewing Angle and Standard LCDs (PDF) outlining Jabil Circuit implementation of Sharp two-way viewing WVGA 800 x 480 thin-film transistor (TFT) using Cyclone FPGAs along with 32-bit Nios II embedded processors and on-chip digital signal processing (DSP) blocks). This cutting-edge technology is feasible by the performance and flexibility of Altera FPGAs.
Figure 3. Dual Video-In Implementation
With a highly efficient device architecture, Cyclone series FPGAs meet the performance and price-level requirements of cost-sensitive routing applications. Complementing this powerful combination is Altera's Nios II embedded processor. No competitive soft processor comes close to matching the performance, utility, and cost-efficiency of a Nios II processor in a Cyclone II series FPGA. Cyclone II series FPGAs and Altera's suite of complementary products and solutions provide unparalleled functionality and pricing that is competitive with ASICs.
For example, you can use Altera’s Flexible Graphics Controller Graphics reference design in the development of an RSE system. This reference design demonstrates the use of Altera Cyclone series FPGAs in a graphics system targeted at the automotive sector. It shows the power and flexibility available in FPGAs for targeting low-cost applications such as those required by the automotive marketplace.