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Embedded and Microcontrollers
Blog Heterogeneous asymmetric multicore processing for always-connected design challenges
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  • Author Author: MAb
  • Date Created: 3 Dec 2014 10:59 AM Date Created
  • Views 513 views
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Heterogeneous asymmetric multicore processing for always-connected design challenges

MAb
MAb
3 Dec 2014

This article was first issued on embedded beat (Freescale blogs)

 

A mixed environment system is one where a multicore system runs a combination of a real-time operating system and a feature-rich operating system.  It’s not a new concept, and there are many examples of products in the industry today, particularly in automotive and high-end industrial. These devices are feature-rich and highly user-interactive, but must respond quickly and reliably to system level events that are driving critical operation of the device.

 

After presenting earlier this month on the topic at ARM TechCon, I was energized to see the level of interest in heterogeneous processing for mixed environment use cases. What’s new is that the underlying hardware architecture for a mixed environment use case, if implemented correctly, can now be used to solve new design challenges like improving energy efficiency of devices that need to stay connected and provide continuous monitoring of environmental inputs. The device itself does not need to be in a high level state of operation because it is essentially just maintaining a network connection (Wi-Fi, Bluetooth, others), processing sensor inputs and is not required to perform heavy processing. But the device must also be able to quickly elevate to a higher state of processing when needed.

 

Split-Shared-Topology

 

What I talked about in my session was the challenge of implementing this type of heterogeneous architecture in a single-chip solution that also provides system flexibility without sacrificing system integrity. System flexibility means that both cores have the ability to access all peripherals and shared memory. This ultimately allows the system to be able to adapt to new application use cases. However, this type of shared bus topology means that both cores now have the ability to access all peripherals and shared memory in the system. So the architecture must provide a way to configure and enforce the safe sharing of system resources.

 

What is the ultimate benefit of this type of heterogeneous architecture?  A more energy-efficient, system-aware device that can also provide a feature-rich user experience and yet not sacrifice on real-time responsiveness.

 

Where does Freescale fit in?


Freescale is no stranger to multicore and heterogeneous processing, but earlier this year we announced that this architecture will be coming to the i.MX 6 series with the first applications processor to integrate an ARMRegistered CortexRegistered- A9 core with an Cortex-M4 core in a single chip design. And, heterogeneous processing will bring new applications and new levels of scalability to the i.MX 6 series which already has a broad footprint and acceptance in the embedded market.

You can see more on the next generation of i.MX 6 series in this short informational video.  (Full product disclosure coming in Q1 2015.)

 

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Amanda McGregor is a product marketer for i.MX applications processors.

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