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Blog Storage Insights #2 - Optimizing your Storage Device
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  • Author Author: bhfletcher
  • Date Created: 20 Jun 2018 3:15 AM Date Created
  • Views 1056 views
  • Likes 6 likes
  • Comments 7 comments
  • hard drive
  • industrial sd
  • memory card
  • storage insights
  • delkin
  • industrial_storage
  • industrial ssd
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Storage Insights #2 - Optimizing your Storage Device

bhfletcher
bhfletcher
20 Jun 2018

Optimizing the Life of Storage Devices

In our first Storage Insights post, we discussed that all SD cards are not equivalent, and how different NAND flash and card technologies can be applied to diverse applications for the same storage form factor.  In this edition, we will examine how the device is written to – in terms of both the controller technology and the application workload – can have a significant impact on the resulting life of the drive.

 

Extending the Life of your NAND Flash Storage Device

To optimize and extend the life of a NAND storage device, we first need to understand how data is written to the device.  Writing to flash is the process of prepping the blocks of the NAND flash and then programming new data to the NAND flash blocks.  New data cannot be saved to flash until the old data is first erased. One complete erasure and programming process of a cell or block of flash is called a program/erase cycle (or P/E cycle.)

Due to the nature of NAND storage, only a finite number of P/E cycles can be performed on a NAND flash before wear makes it unreliable to store data.  One way of extending the life of your flash device is to utilize the available P/E cycles more efficiently. Some options that could help would be to reduce unnecessary copying of files or downloading of data or consolidating writes.

Understanding your usage model can also impact your P/E cycle count.  Data written to your storage device is done either sequentially (no seeks, lots of continuous I/O) or randomly (seek-write-seek-write, etc.)  Sequential writing will provide a more efficient write performance (lower write amplification) for the flash which will improve the life of the flash NAND.

 

Reducing P/E Cycle Breakdowns with Wear Leveling

As discussed, NAND flash devices can only undergo a limited number of program/erase cycles, and in most cases, the flash media are not used evenly. If some areas are updated more frequently than others, the lifetime of the device will be reduced significantly. Thus, Wear Leveling is applied to extend the lifespan of NAND flash by evenly distributing P/E cycles across the media.

Delkin utilizes advanced Wear Leveling algorithms, which can efficiently distribute flash usage through the whole flash media area regardless of the operating system, file system or partition structure on the drive. By implementing both dynamic and static Wear Leveling algorithms, which will wear level data that is updated frequently as well as that which is never updated, the life expectancy of the NAND flash is greatly improved.

 

Utilizing SMART Data

Another recommendation to improve and track the life of your drive is to utilize your drives’ available SMART (Self-Monitoring and Reporting Technology) data.  Customers can regularly obtain data about the estimated remaining life in a flash device, spare block status, and how many P/E cycles have been consumed*. Utilizing this information will allow the user to evaluate the read/write operations and make changes accordingly.  This is an especially valuable tool during the development phase, when software can be modified and optimized.

 

Proactive Read Disturb Refresh

Read disturb errors occur when too many reads are made to a page without an intervening block erase, which has become more of an issue as flash geometries have shrunk. If your application is read-intensive, then it is vital to have a flash controller with a read disturb management system that will proactively refresh blocks before bit errors accumulate beyond the correction ability of the ECC engine. Whether a read counter or other mechanism is used to trigger the refresh, the data will be moved to a freshly erased block, and then the erased block can be put back into service.  If proactive read refresh is not employed in a read-intensive application, then the chance of UECC’s, premature bad blocks and data loss is increased.

 

Block Base vs Page Base Mapping

Understanding the controller mapping technology relative to the flash structure is another key factor in NAND flash optimization. Block-based mapping is usually employed on devices with no DRAM (i.e. CompactFlash, SD cards & USB drives), whereas page-based mapping is typical on SSD’s. The impact of block-based firmware is a potentially higher Write Amplification Factor (WAF) which consumes P/E cycles and wears out the drive more quickly.  However, there are many factors to consider when evaluating page-based vs. block-based – such as the flash type, the performance needed and the write model (sequential vs. random.) To see an example of block base vs page based writing, visit: https://www.delkin.com/technology/flash-endurance/

 

To Learn More

Look for the next Storage Insights post soon, if you missed Storage Insights #1, check it out here,

and feel free to ask a question or reach out to Delkin with any storage questions in the meantime

Delkin Devices or https://www.delkin.com/contact/ 

 

*SMART data varies by product family – not all data is available on all devices.  Method for extracting data also varies by product and interface.

 

Buy Delkin CompactFlashBuy Delkin CompactFlash

 

Buy Delkin mSATABuy Delkin mSATA

 

Buy Delkin microSDBuy Delkin microSD

 

Buy Delkin SDBuy Delkin SD

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Top Comments

  • dougw
    dougw over 4 years ago in reply to DAB +1
    My understanding is that the FET state is dictated by the charge on the gate. They are very small gates so there isn't much charge. These gates are completely isolated by non-conductive oxide, so the charge…
  • DAB
    DAB over 4 years ago in reply to dougw +1
    Hi Douglas, I was curious as I am looking into a new view of how these semiconducting devices work at the atomic level. I think you are aware of my theory that photon flow, not electron flow makes these…
  • drozwood90
    drozwood90 over 3 years ago +1
    As a follow up, we have quite a few Articles in this series covering a variety of topics! Here are links to all the blog posts if you are interested: Storage Insights #1 - Why Not All SD Cards are Created…
  • drozwood90
    drozwood90 over 3 years ago

    As a follow up, we have quite a few Articles in this series covering a variety of topics!

    Here are links to all the blog posts if you are interested:

    Storage Insights #1 - Why Not All SD Cards are Created Equal

    Storage Insights #3 -Technical Guide for CompactFlash (CF) and Secure Digital (SD) Cards

    Storage Insights #4 - NAND Flash Based SSD Drives and the Flash Controller

    Storage Insights #5- Guide to Embedded Multimedia Card (eMMC)

    Storage Insights #6 - Guide to SATA (Serial ATA)

    Storage Insights #7 - SD Card Technology Advantages

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  • DAB
    DAB over 4 years ago in reply to dougw

    Hi Douglas,

     

    I was curious as I am looking into a new view of how these semiconducting devices work at the atomic level.

    I think you are aware of my theory that photon flow, not electron flow makes these devices work.

     

    When you combine the various layers on a substrate you get locations where the different atoms create a surplus or deficit of photons in the shell of each atom. The number of atoms over a given area then dictates charge flow abilities.

     

    From the descriptions provided I think we are looking at a physical issue in which the flow of photons causes the individual atoms to migrate across the substrate changing the overall distribution of active atoms and thus change the entire characteristics of the device.

     

    DAB

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  • dougw
    dougw over 4 years ago in reply to DAB

    My understanding is that the FET state is dictated by the charge on the gate. They are very small gates so there isn't much charge. These gates are completely isolated by non-conductive oxide, so the charge doesn't bleed off. To change the state of the FET, the charge on the gate needs to be increased or depleted. This is done by using enough voltage to break down the oxide, allowing charge to pass through it using the Fowler-Nordheim tunnelling effect for erasure and HEI phenomenon for writing.

    With enough charge changing cycles the very thin oxide starts to lose its insulating abilities and the transistor state becomes unreliable. I don't know if it is due to physical pitting or if some of the oxygen bonds are broken.

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  • delkinindustrial
    delkinindustrial over 5 years ago in reply to DAB

    While Delkin Devices does not design or manufacture the NAND devices, we integrate flash components from multiple manufacturers into our storage products.  Therefore, the physics of the design, the wear effects and resulting specifications would be unique to each individual NAND manufacturer.   The phenomenon of flash wear is well documented, and of course, with each successive geometry shrink, the challenges of endurance and data retention only become greater.

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  • DAB
    DAB over 5 years ago in reply to delkinindustrial

    Does the oxide layer issue have a solution?

    I would think that there are materials that would give you the same storage capability without degrading physically with each charge/discharge cycle.

     

    I would love to see the physics of your design so I can study the effect.

    Do you have any notes on how you tested the devices and found the problem?

     

    By the way, I do research into the subatomic structure of materials in my spare time, so I get really curious when these types of issues arise.

     

    DAB

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