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Circuit Diagram is needed for the following features

Former Member

I have to design a crcuit which will have following features:

 

        I/P: X15 X14 X13... ... ...X0 bits

        O/P: 1, when I/P bit sequence has 3 consecutive ones

           or atleast 3 consecutive ones.

 

Would u pls show me the circuit diagaram needed for this requirement?

 

thanx in advance

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    Can't be much simpler: 14 three-input NANDs, each connected to three successive input bits:

    X15, X14, X13 => NAND13;

    X14, X13, X12 => NAND12;

    .

    .

    .

    X2, X1, X0 => NAND0;

     

    Then the 14 outputs get NANDed together via a 14 input NAND.

     

    Output goes high if and only if three or more successive bits are high.

     

    All of which should fit nicely in any tiny CPLD, PAL, etc. A one-chip fast, unclocked solution.

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  • 0

    Can't be much simpler: 14 three-input NANDs, each connected to three successive input bits:

    X15, X14, X13 => NAND13;

    X14, X13, X12 => NAND12;

    .

    .

    .

    X2, X1, X0 => NAND0;

     

    Then the 14 outputs get NANDed together via a 14 input NAND.

     

    Output goes high if and only if three or more successive bits are high.

     

    All of which should fit nicely in any tiny CPLD, PAL, etc. A one-chip fast, unclocked solution.

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