State of micro pins when in sleep mode

This may be an obvious question, If I am using a micro. (Normally Microchip devices) and I have a pin set high. If I put the micro to sleep, does this pin stay hi or do all the pins go low ?

Background is I want to measure a battery voltage that also powers the micro.If this drops to a low value, I want the micro to go to sleep, and enable a FET. i.e switch on an output pin.

This FET switches out the potential divider that I'm using to measure the battery voltage with the micro.

The leakage current of the circuit is then reduced.

Thanks

Former Member over 16 years ago

A PICs general output pins remain in their previous state - hi, low, input, analogue - while in sleep.

If you're saving power, be sure to turn off the ADC, USART, comparitor voltage reference and pullups, too.
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Former Member over 16 years ago in reply to Former Member

Andy,

Appreciate the reply. Thanks.
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Former Member over 16 years ago

...just a thought - if your pic is powered directly from the battery, rather than using an external potential divider, does the device have a voltage reference module?

Many of the PICs have a fixed 0.6v reference. If you measure this (see the ADC input selection section to see if VRef can be selected on the multiplexer) you can deduce the PIC supply voltage: ( 0.6 / Reading ) * 256 when using an 8 bit ADC value.
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Former Member over 16 years ago in reply to Former Member

Andy,

Useful tip. Thanks.

The micro I'm using is the PIC16F506-I/STPIC16F506-I/ST, however the battery supply is 3 Li-Ion cells approx 10.8V.

The battery supply is reduced to 3.3V via a regulator. The potential divider is across the 3 cells so I dont think I can use the method above.

My thought is that an inline N-channel Fet on the P.D when switched off will 'isolate' the leakage across the P.D.

Any other ideas appreciated !

Thanks
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Former Member over 16 years ago in reply to Former Member

I may be missing something in the design but if the fet is in effect disconnecting the bottom of the divider, Vbat would appear on the input pin?

The datasheet suggests Vdd + 0.3v as the maximum voltage on any pin, so you'll probably still have current flowing through the divider, but into the pic rather than the lower half of the divider.
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Former Member over 16 years ago in reply to Former Member

Andy,

I guess I need to actually protoype my thought on this but attached is the concept. Supply and regulator for pic not shown.

Pin 6 reads the analogue measurement of battery when Pin 7 is active.

When 7 is low, Q1 is off and therefore I was thinking leakage of the divider is removed.

I may have missed the obvious however !

Thoughts?

File attached

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Former Member over 16 years ago in reply to Former Member

Yup, sorry, that's fine, carry on!
I wasn't sure if you intended connecting pin 6 above or below Q1.
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