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Vertical counter switch debouncing; has anyone used this in a design?

Catwell

Vertical Counter switch debouncing just uses a time delay for dealing with switch debounce. After giving it a try in a PIC project of mine, I found it to be a huge waste of clock cycles.


Is there any real benefit of the Vertical Counter?

  • Hi Cabe,

    A 10 ms delay and retest for the same signal condition only confirms that the input is genuine input and not noise.

    Your concern for lost clock cycles is also genuine. If you can utilize the delay time for some fixed routines within the delay loop, then you are optimizing the code.

    Great thinking.