Cooler Runner CPLD

Question

So I am starting to mess with CPLD's more than I did in college and I wanted to write look up tables into the onboard memory of the cool runner. I am not sure how to go about doing this.My intent is to make a "poor man's" function generator. I want to make out the clock speed of the CPLD and use a lookup table to create my sine wave. I'm using the ISE Design Suite 14.7. Any help would be great.

johnbeetem · Accepted Answer

I could be wrong, but as far as I know none of the Xilinx CoolRunner chips have look-up tables. CoolRunner is a PAL or PLA architecture, so optimized for wide product terms rather than memory. There are no distributed or block RAMs. You can use CPLD macrocells for any purpose -- including ROMs -- but they don't implement ROMs efficiently and you'll run out quickly.

You'd probably be better off with a small FPGA, such as the Lattice iCE40 series which have 4-input LUTs and 4096-bit block RAMs. It has nice development board that's only US$21 in the USA: http://www.element14.com/community/docs/DOC-55683/l/lattice-semiconductor-ice40hx1k-stick-evn-icestick-evaluation-kit

You might also get more response to this discussion if you (or an admin) moves it to the more appropriate http://www.element14.com/community/groups/fpga-group