CPLD Finite State Machine and Internal Signals

Hi all,

I am using Altera Quartus 14.1 with a MAXV CPLD. I would like some assistance with driving a state machine using internal input and output signals as opposed to real inputs and outputs? I want to have my state machine enabled/disabled by an internally generated flag and I would also like to set internal flags within the CPLD instead of driving real world output pins. Does anyone have a method or way ahead that might allow me to get this working?

Regards, oldmanraskers

Top Replies

michaelkellett over 10 years ago in reply to oldmanraskers +1

If it's your first design with this kind of part it might be a good plan to have a simulation running and the design fitted into the chip using the right pins before you commit to the board being made…

Parents

0 michaelkellett over 10 years ago

What tools are you using for your design - what you describe is easy in VHDL or Verilog.

I can help you with VHDL, others can probably help with Verilog.

MK
Cancel
Vote Up 0 Vote Down

Sign in to reply

Verify Answer

Cancel

Reply

0 michaelkellett over 10 years ago

What tools are you using for your design - what you describe is easy in VHDL or Verilog.

I can help you with VHDL, others can probably help with Verilog.

MK
Cancel
Vote Up 0 Vote Down

Sign in to reply

Verify Answer

Cancel

Children

0 oldmanraskers over 10 years ago in reply to michaelkellett

I have used the built in State Machine design tool and converted the design file to VHDL. I think I'm probably missing the point with what STD_LOGIC declarations mean. I'm basically trying to have a state machine that is started by pressing a momentary start pushbutton that I latch using a flip flop, but I want the state machine to run once and then stop, until the start pushbutton is pressed again. I thought that I could tell the state machine to set an output in the last state, and use that output to disable the latched start circuit but the software seemingly won't let me check the state of an output - which kind of makes sense - but I don't know how to fix it because the only option I have for output bits is OUT STD_LOGIC.
Cancel
Vote Up 0 Vote Down

Sign in to reply

Verify Answer

Cancel
0 michaelkellett over 10 years ago in reply to oldmanraskers

Please post the VHDL code - I'll take a look.

Which MaxV device are you using and do you have hardware to run your design on.

MK
Cancel
Vote Up 0 Vote Down

Sign in to reply

Verify Answer

Cancel
0 oldmanraskers over 10 years ago in reply to michaelkellett

I'm just designing the hardware circuitry at the moment, so I guess I'll leave this issue until that's finished.
Cancel
Vote Up 0 Vote Down

Sign in to reply

Verify Answer

Cancel
0 michaelkellett over 10 years ago in reply to oldmanraskers

If it's your first design with this kind of part it might be a good plan to have a simulation running and the design fitted into the chip using the right pins before you commit to the board being made. People often get caught out by odd restrictions on the use of certain pins which may be for clock inputs, global resets, input only etc.

MK
Cancel
Vote Up +1 Vote Down

Sign in to reply

Verify Answer

Cancel