Fast modulation based on analog signal: FPGA worth it?

There are quite a few things you have not specified that might affect your choice, but I suspect than an FPGA will be the best way to do it.

How does the analogue signal vary, if you want to detect small changes in amplitude of a 1MHz signal you will need to sample very fast, if the signal is non repetitive you will need to use a non pipelined ADC so you can respond to the change of input quickly enough.

So it would help to have a  diagram of the extreme case of signal and U1 and U2.

From an FPGA point of view, it's all easy - the hard part will be the ADC and DAC - do you have to have 16 bit resolution, and have you ever designed with a 10MHz+ 16Bit ADC ?

If you could get away with 12 bit ADCs running at effective rate of 7.2MHz you can do it using a micro processor (STM32F767), the built in DAC may not be fast enough. It will be hard to write the code to deall with the data fast enough.

MK

Pascal,

Where I think that Michael's approach makes sense, I think I would turn the problem around and do it more in the analog domain.  I would use a pair of voltage comparitors to generate the shutter signals.  You could use a pair of DACs to set the thresholds for the high and low values of the window.  Computationally, this would greatly reduce the complexity of your design.

Good luck!

Gene

Thank you for your answer Michael!

The analogue signal is not repetitive. The change is in voltage and between -10 V and 10 V. I already found some ADCs which can sample with several 100 MS/s.

Regarding the U1 and U2 digital signal: You can imagine them to be the lower and upper barrier of an interval. When the analogue voltage is above U1 the shutter will be opened, and as soon as the analogue voltage is above U2 the shutter will be closed. The array of U1s and U2s will be provided by the computer which is connected to the FPGA. This array is user defined and arbitrary.

Unfortunately I have to have at least 14 bit and since the effective number of bits seems to be a bit lower in reality and we don't want to run into boundaries we thought that 16 bit should be suitable for our specifications. Sadly, I have never worked with an FPGA or ADC, this is my first time.

If there is still something unclear, please contact me.

PK

Hey Gene,

we also thought about working more in the analog domain. The problem I saw with that solution was the sheer amount of data, which the voltage comparator has to process. In extreme cases only the U1 and U2 data from the computer can be up to 1 TB.

For the setup 2 galvanometer mirrors will be used. So the shutter signal should only be open if both mirrors are in the given range. Wouldn't the design of such an analogue processing unit be pretty complex?

However, I understand your argument regarding the computationally complexity. I will once again think about the analog solution.

Thank you very much for your help!

Pascal

I'm not sure what resources you have available but designing a system that can sample 16 bits at as high as 50MHz with 20ns latency is a big undertaking, I'm currently working on a system that will sample 8 channels at 10MHz and stream data to Gb Ethernet, it will take about 4000 hours of experienced hardware, software and FPGA engineers' time to develop.

What is the shortest time the shutter will be open or closed ?

How quickly are U1 and U2 updated.

MK

You first have to decide what "worth it" means to you.

Are you looking to build a one of device or a product.

What are the other options you could use?

Once you define your end goals, then you can do a sensible cost/benefit analysis to decide if the project has a reasonable solution space.

DAB

Hi Michael,

I was looking at FPGA Mezzanine Cards (FMC) which can be added on a FPGA board and offer efficient ADCs. One producer that could offer this would be from ABACO (https://www.abaco.com/products/fmc144-fpga-mezzanine-card). This comes at the cost of a lot of money which has to be spent on the hardware. The budged would allow this, however I don't want to just throw money at a problem which could be solved more efficiently.

The shortest time for the shutter to be open or closed would be around 0,5 µs.

In the worst case this would also be the update time for U1 and U2. These voltages have to be updated as soon as the galvanometer is at a given position (i.e. has a certain voltage on its output).

Thank you once again for your time!

PK

Are you able to tell us which galvanometer you will use - I couldn't find one that was anything like that fast.

MK

Sorry, I think we have a misunderstanding here: The voltages U1 and U2 will be provided by the computer for the comparison. The voltage coming from the galvanometer is U_in (analog). The galvanometer just scans the object and meanwhile the FPGA (or whatever will be used) checks if the voltage, which translates to the galvanometer position, is in the voltage range which will be given by the computer.

Just because the voltages U1 and U2 could possibly change really fast does not mean that the galvanometer has to be incredibly fast because we could also chose really small voltage differences between U1 and U2. However, we want the Galvo to be as fast as possible, of course.

Does that make it clear or did I possibly misunderstand your question?

PK

I'm trying to understand your system because I think you are going up a blind alley.

No mechanical device can output meaningful position data with anything like the bandwidth of the data conversion board you quoted (370Msamples at 11 ENOB). The best galvo I could find claims to settle (for small step change) in 100us.

I don't think I can offer any very useful advice without a much better understanding of the system.

I can tell you that if you really do need 300Mhz+ rate ADC then an FPGA is the only way you could possibly control this system, no micro is anything like fast enough and trying to process 16 bit data paths at this speed with small scale logic wouldn't be practical or cost effective.

MK