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Get Your Xilinx FPGA/Programmable SoC Questions Answered here

rscasny

In the past year or so, the element14 community has been offering quite a few programs, contests, and initatives around Xilinx's FPGA and heterogeneous SoC, ZYNQ. We have hosted webinars, run roadtests, and offered a training program last year called Path to Programmable.

 

I see element14 member interest in Xilinx product knowledge on the rise. I plan on offering more Xilinx-related projects and roadtests in the coming months. (Stay tuned to Path to Programmable 2 with the Ultra96v2) Given all this activity, I thought it would be a great idea to bring in a Xilinx product expert for some well needed Q&A time. So let me introduce you to Adam Taylor ( ).

 

I believe Adam has been an element14 member for several years. He is the Director of ADIUVO Engineering. He is a Chartered Engineer and Fellow of the Institute of Engineering and Technology. He is well known for his Microzed Chronicles. He writes the Exploring the Programmable World for element14. Adam has been instrumental in developing element14's FPGA/Programmable SoC Essentials.

 

Adam also is an expert in the PYNQ framework: Python for ZYNQ productivity. So, if you are asoftware developer who wants to explore the Programmable world, I'd encourage you to ask Adam your top questions.

 

So, if you have any questions revolving around FPGAs, programmable SoCs, a project in progress, perhaps even a question about Vivado, please click REPLY and asked them here.

 

Sincerely,

 

Randall Scasny

-element14 Team

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  • This question is for   -

     

    I'm one of the trainees in the Path II Programmable course.  I'm encountering an issue that hopefully you've seen before.  At the end of HW Lab7 when I am trying to write the bitstream for the design with new IP added, synthesis runs successfully but implementation fails during optimization.

     

    Here is an excerpt from the impl/runme.log:

     

    Starting Logic Optimization Task

     

    Phase 1 Generate And Synthesize Debug Cores

    INFO: [Chipscope 16-329] Generating Script for core instance : dbg_hub

    INFO: [IP_Flow 19-3806] Processing IP xilinx.com:ip:xsdbm:3.0 for cell dbg_hub_CV.

    ERROR: [IP_Flow 19-3805] Failed to generate and synthesize debug IPs.

    ERROR: [Common 17-161] Invalid option value '0' specified for '-jobs'.

    ERROR: [Chipscope 16-330] Synthesis of Debug Cores has failed

    Phase 1 Generate And Synthesize Debug Cores | Checksum: 24bc6163a

     

    Time (s): cpu = 00:01:01 ; elapsed = 00:03:50 . Memory (MB): peak = 2532.340 ; gain = 1.000 ; free physical = 1191 ; free virtual = 3762

    INFO: [Common 17-83] Releasing license: Implementation

    17 Infos, 0 Warnings, 0 Critical Warnings and 3 Errors encountered.

    opt_design failed

    ERROR: [Chipscope 16-338] Implementing debug Cores failed due to earlier errors

    INFO: [Common 17-206] Exiting Vivado at Tue Oct 22 20:02:55 2019...

     

    I can send you the full synth and impl logs if that will help.  I saw on the Xilinx forum that this could be related to the version of Ubuntu installed.  I wanted to check with you before I go through trying to install another version.  Here is the link to the forum https://forums.xilinx.com/t5/Implementation/Invalid-option-value-0-specified-for-jobs/td-p/881190

     

    I am running Ubuntu 16.04.6 in the VM.

     

    I also tried running the tcl command "check_ip_cache -clear_output_repo"

     

     

     

     

    Thanks,

     

    Ralph

Reply

  • This question is for   -

     

    I'm one of the trainees in the Path II Programmable course.  I'm encountering an issue that hopefully you've seen before.  At the end of HW Lab7 when I am trying to write the bitstream for the design with new IP added, synthesis runs successfully but implementation fails during optimization.

     

    Here is an excerpt from the impl/runme.log:

     

    Starting Logic Optimization Task

     

    Phase 1 Generate And Synthesize Debug Cores

    INFO: [Chipscope 16-329] Generating Script for core instance : dbg_hub

    INFO: [IP_Flow 19-3806] Processing IP xilinx.com:ip:xsdbm:3.0 for cell dbg_hub_CV.

    ERROR: [IP_Flow 19-3805] Failed to generate and synthesize debug IPs.

    ERROR: [Common 17-161] Invalid option value '0' specified for '-jobs'.

    ERROR: [Chipscope 16-330] Synthesis of Debug Cores has failed

    Phase 1 Generate And Synthesize Debug Cores | Checksum: 24bc6163a

     

    Time (s): cpu = 00:01:01 ; elapsed = 00:03:50 . Memory (MB): peak = 2532.340 ; gain = 1.000 ; free physical = 1191 ; free virtual = 3762

    INFO: [Common 17-83] Releasing license: Implementation

    17 Infos, 0 Warnings, 0 Critical Warnings and 3 Errors encountered.

    opt_design failed

    ERROR: [Chipscope 16-338] Implementing debug Cores failed due to earlier errors

    INFO: [Common 17-206] Exiting Vivado at Tue Oct 22 20:02:55 2019...

     

    I can send you the full synth and impl logs if that will help.  I saw on the Xilinx forum that this could be related to the version of Ubuntu installed.  I wanted to check with you before I go through trying to install another version.  Here is the link to the forum https://forums.xilinx.com/t5/Implementation/Invalid-option-value-0-specified-for-jobs/td-p/881190

     

    I am running Ubuntu 16.04.6 in the VM.

     

    I also tried running the tcl command "check_ip_cache -clear_output_repo"

     

     

     

     

    Thanks,

     

    Ralph

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