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Embedded and Microcontrollers
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Embedded and Microcontrollers
Embedded Forum Get Your Xilinx FPGA/Programmable SoC Questions Answered here
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Related

Get Your Xilinx FPGA/Programmable SoC Questions Answered here

rscasny
rscasny over 6 years ago

In the past year or so, the element14 community has been offering quite a few programs, contests, and initatives around Xilinx's FPGA and heterogeneous SoC, ZYNQ. We have hosted webinars, run roadtests, and offered a training program last year called Path to Programmable.

 

I see element14 member interest in Xilinx product knowledge on the rise. I plan on offering more Xilinx-related projects and roadtests in the coming months. (Stay tuned to Path to Programmable 2 with the Ultra96v2) Given all this activity, I thought it would be a great idea to bring in a Xilinx product expert for some well needed Q&A time. So let me introduce you to Adam Taylor ( adamtaylorcengfiet ).

 

I believe Adam has been an element14 member for several years. He is the Director of ADIUVO Engineering. He is a Chartered Engineer and Fellow of the Institute of Engineering and Technology. He is well known for his Microzed Chronicles. He writes the Exploring the Programmable World for element14. Adam has been instrumental in developing element14's FPGA/Programmable SoC Essentials.

 

Adam also is an expert in the PYNQ framework: Python for ZYNQ productivity. So, if you are asoftware developer who wants to explore the Programmable world, I'd encourage you to ask Adam your top questions.

 

So, if you have any questions revolving around FPGAs, programmable SoCs, a project in progress, perhaps even a question about Vivado, please click REPLY and asked them here.

 

Sincerely,

 

Randall Scasny

-element14 Team

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Top Replies

  • jomoenginer
    jomoenginer over 6 years ago +4
    Awesome! It's great that adamtaylorcengfiet is a resource on element14 for Programmable SoC questions. I'm sure I will have many as I finish my Digilent Zybo Z7 RoadTest. I do find Adam's Microzed Chronicles…
  • jomoenginer
    jomoenginer over 6 years ago +4
    For what it's worth, there is an Integrating Arm Cortex-M soft CPU IP into FPGAs virtual workshop that features Adam Taylor as an instructor and uses the Digilent Arty S7-50T to be held August 14th, 2019…
  • wolfgangfriedrich
    wolfgangfriedrich over 6 years ago +3
    I would appreciate any comments on a process on how to make the DDR3 SDRAM MIG work without using the AXI interface in VHDL. As a target platform I have the Digilent Arty S7 board. I tried this during…
  • wolfgangfriedrich
    wolfgangfriedrich over 6 years ago

    I would appreciate any comments on a process on how to make the DDR3 SDRAM MIG work without using the AXI interface in VHDL. As a target platform I have the Digilent Arty S7 board.

    I tried this during my Roadtest of the Arty S7 but was not successfull and really like to revisite this.

    Thanks,

    - W.

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  • jomoenginer
    jomoenginer over 6 years ago

    Awesome!  It's great that adamtaylorcengfiet is a resource on element14 for Programmable SoC questions.  I'm sure I will have many as I finish my Digilent Zybo Z7 RoadTest.  I do find Adam's Microzed Chronicles quite useful though.  

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  • adamtaylorcengfiet
    adamtaylorcengfiet over 6 years ago in reply to wolfgangfriedrich

    What do you mean without using VHDL? Have you tried dragging and dropping the DDR memory block from the boards element of the properties onto the block diagram?

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  • adamtaylorcengfiet
    adamtaylorcengfiet over 6 years ago in reply to jomoenginer

    Really glad you find them useful image Thanks for reading them

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  • wolfgangfriedrich
    wolfgangfriedrich over 6 years ago in reply to adamtaylorcengfiet

    Sorry, my typing is unclear. I meant: not using the AXI as interface, and using VHDL as my language of choice. 

    I have never used block diagrams and graphical input in Vivado and intend to keep it that way. image

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  • jomoenginer
    jomoenginer over 6 years ago in reply to wolfgangfriedrich

    Looking at the block diagram for the Zynq-7000 SoC, the Memory Interfaces, including the DDR3, is connected to the PL via a AXI 32-bit, so it would be interesting if this is directly accessible without going through the AXI.

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  • wolfgangfriedrich
    wolfgangfriedrich over 6 years ago in reply to jomoenginer

    My board is the Arty-S7. It has 'only' a Spartan7 FPGA not a Zync SoC. So I need an IP core to connect to the DDR3.

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  • Fred27
    Fred27 over 6 years ago

    I didn't want to clog up this thread with general comments other than questions, but I have to agree with jomoenginer - it's great that adamtaylorcengfiet is here on E14 to help. The MicroZed Chronicles are an amazing source of information and inspiration on all things Zynq.

     

    When I have a question that isn't totally dumb, I'll be sure to ask!

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  • adamtaylorcengfiet
    adamtaylorcengfiet over 6 years ago in reply to wolfgangfriedrich

    The arty S7 has a MIG file with it which will set up for the DDR3 on the board. However the easiest way to generate this is to use the IP integrator flow and drag and drop the DDR from the external memory on to a block diagram. This will configure the MIG for the Arty DDR.

     

    However, I know you want to work with VHDL flow, so once you have done this I would then generate a VHDL / Verilog wrapper and just include that wrapper in your VHDL file.

     

    image

     

    To do this make all the IO external - by selecting the MIG and right clicking and saying make external

    image

    Then you can create a VHDL / Verilog Wrapper - you should be able to use this in your VHDL design

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  • platin21
    platin21 over 6 years ago

    I wonder if somebody did already make a PCIe driver for the AxiEthernet via the XDMA?

    I feel so lost.

    It's incredbliy hard to get it right as of the interrupts and that it loses the completed count e.g sometimes i get a race between driver and fpga.

    We got the TX Path working but the RX seems to just not care about any packet arriving…

    We are using the arty 7.

    But maybe this is the wrong place to ask…
    (Can't get a FAE sadly as the contact was lost.)

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>
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