Memory Quiz

Didn't like this quiz at all. Even more manufacturer specific than usual and several subjective questions.

I don't think that even DDRAMs own mother would rate it as having a straightforward architecture. !!

(Try designing a controller for it)

Or for multi channel DDR5 ...

Performance - yes, simplistic architecture - no.

MK

michaelkellett mike, DRAM controllers are bitches to build from scratch. By off the shelf!

Or if you like the challenge see this article.
~~ Cris

I took the challenge as a teenager with successful results in the early 1980's when TI just released their single voltage 4164 64Kx1 DRAM.

It worked seemlessly with the Zilog Z80 and a tiny bit of glue logic or with TI's TMS4500 DRAM Controller.

A few years around 1987 later we used 384K - 1.5M of DRAMs with the updated TMS4502 DRAM Controller for a dual 68000 CPU Laser printer controller. Those PCBs were very large and about the size of a small coffee table.

With both solutions one critical element is signal integrity using controlled impedance often with 33 ohm series termination resistors.  This because the DRAMs signals were continually in action and the length of the traces warranted attention. The other was providing clean power with a suitably designed PDN (power distribution network) because there was a lot of current being shunted around to replenish the DRAM capacitors.

Just like now, back then SRAM (Static RAM) was much simpler to implement, consumes considerably less power but not used because of their considerably lower lower storage density and higher cost.

I have designed controllers for SDRAM in FPGA with modest clock speeds (up to 100MHz or so.).

I've used DDRAM IP from the manufacturer in FPGA and it's altogether a different beast.

The paper you referenced is concerned with those nice simple old fashioned SDRAMs. (Single data rate)

With a modern DDRAM (double data rate) you need to phase lock and delay a sampling clock to maintain  sampling jitter levels below as little as 100 - 200ps

and position the sampling window centre within low 10s of ps. This requires hardware level interfaces in the FPGA and the use of the manufacturers' IP to

control them.

The problems arise if you want to do something unusual.

Most DRAM controllers are optimised for reading and writing quite small chunks of data, maybe 256 bits at time.

If you want to do a burst read, which the memory chip may support, of maybe 16384 bits, then you need to design your own controller. This is quite

feasible with SDRAM but a much bigger task with a modern DDRAM.

MK

I have designed controllers for SDRAM in FPGA with modest clock speeds (up to 100MHz or so.).

I've used DDRAM IP from the manufacturer in FPGA and it's altogether a different beast.

The paper you referenced is concerned with those nice simple old fashioned SDRAMs. (Single data rate)

With a modern DDRAM (double data rate) you need to phase lock and delay a sampling clock to maintain  sampling jitter levels below as little as 100 - 200ps

and position the sampling window centre within low 10s of ps. This requires hardware level interfaces in the FPGA and the use of the manufacturers' IP to

control them.

The problems arise if you want to do something unusual.

Most DRAM controllers are optimised for reading and writing quite small chunks of data, maybe 256 bits at time.

If you want to do a burst read, which the memory chip may support, of maybe 16384 bits, then you need to design your own controller. This is quite

feasible with SDRAM but a much bigger task with a modern DDRAM.

MK