Have a question about ADCs or DACs? Ask our Expert, Nick Gray

I am sorry that I somehow missed your question.

Yes, some manufacturers of FPGAs are attempting to implement ADCs in their FPGAs. My personal feeling is that this will be a little difficult for them to do because the digital noise generated by the gates will cause the die substrate (on-chip common) to be quite noisy, which will add noise to the ADC conversion. Noise will most probably also find its way into the ADC reference voltage, further exacerbating the noise problaem. There are ways to get around this, however, but the result in any case is a relatively low conversion rate. Cost wise it should be beneficial to the end user, especially since more than one company is doing this and competition should keep the cost down. Performance is another story. If the ADCs are 8 or perhaps 10 bit resolution, there should be little problem with reasonable performance, although a stand-alone ADC should perform better than an imbedded one. At resolutions of 12 bits and more, I believe that performance will be no better than perhaps 10 bits.

What this means is, basically, that only the most significant 8 to 10 bits will be reliable, with the rest being mostly noise. The way around this would be to average many samples, but I doubt that this will increase performance beyond the 12 bit level, or 14 bit level at the most. And this would be satisfactory for most applications. Another approach would be to use converter topology that is relatively immune to noise, like a multi-slope ADC.

The problem I see is that there may not be provision to adjust for the offset and gain error of the ADC and the manufacturers will have the task of being sure that the user knows how to do this to prevent a lot of complaints and disgruntled users. These companies are digital and may not appreciate the analog problems unless they hire the right analog engineers. Some of the offset and gain errors can be done with conditioning circuitry before the ADC input of the FPGA, but these errors can vary from one individual part to another, so could probably more effectively be handled in the system processor.

As for applications where this might be beneficial, any system that takes input from the outside world and needs the versatility of an FPGA could potentially benefit.

I am sorry that I somehow missed your question.

Yes, some manufacturers of FPGAs are attempting to implement ADCs in their FPGAs. My personal feeling is that this will be a little difficult for them to do because the digital noise generated by the gates will cause the die substrate (on-chip common) to be quite noisy, which will add noise to the ADC conversion. Noise will most probably also find its way into the ADC reference voltage, further exacerbating the noise problaem. There are ways to get around this, however, but the result in any case is a relatively low conversion rate. Cost wise it should be beneficial to the end user, especially since more than one company is doing this and competition should keep the cost down. Performance is another story. If the ADCs are 8 or perhaps 10 bit resolution, there should be little problem with reasonable performance, although a stand-alone ADC should perform better than an imbedded one. At resolutions of 12 bits and more, I believe that performance will be no better than perhaps 10 bits.

What this means is, basically, that only the most significant 8 to 10 bits will be reliable, with the rest being mostly noise. The way around this would be to average many samples, but I doubt that this will increase performance beyond the 12 bit level, or 14 bit level at the most. And this would be satisfactory for most applications. Another approach would be to use converter topology that is relatively immune to noise, like a multi-slope ADC.

The problem I see is that there may not be provision to adjust for the offset and gain error of the ADC and the manufacturers will have the task of being sure that the user knows how to do this to prevent a lot of complaints and disgruntled users. These companies are digital and may not appreciate the analog problems unless they hire the right analog engineers. Some of the offset and gain errors can be done with conditioning circuitry before the ADC input of the FPGA, but these errors can vary from one individual part to another, so could probably more effectively be handled in the system processor.

As for applications where this might be beneficial, any system that takes input from the outside world and needs the versatility of an FPGA could potentially benefit.