I am using Xilinx ZCU208 evaluation board with Simulink HDL IP Core Generation design process. The CLK104 board that comes with the ZCU208 uses the onboard 10 MHz reference clock as default. With the Avnet RFSoC Explorer, I can interactively configure the CLK104 to use external 10 MHz clock. I need to configure the LMK reference clock configuration to use the external 10 MHz clock. How do you configure the source of the 10 MHz reference clock in the Simulink design flow with the ZCU208 board?
