I don't quite understand what you're asking if you're asking anything. If you mean a reference application, the Vivado design suite supports Open IP Example Design flow for the Memory Interface Generator (MIG 7 series) IP, you can choose verilog or VHDL code.
I don't quite understand what you're asking if you're asking anything. If you mean a reference application, the Vivado design suite supports Open IP Example Design flow for the Memory Interface Generator (MIG 7 series) IP, you can choose verilog or VHDL code.
