Hello,
We are currently evaluating the AD7192 ADC as a replacement for the obsolete CS5532 in our load cell application.
With the CS5532, after system calibration, we were able to achieve full-scale output at an input of 10 mV. While testing the AD7192, we are observing behavior that does not fully align with the system calibration input span specifications given in the datasheet.
Our configuration is as follows:
- Reference voltage (Vref): 5 V
- Gain: 128
- Calculated full-scale input range (FS): 39 mV
As per the datasheet, the allowable input span for system calibration is:
- Minimum input: 0.8 × FS ≈ 31 mV
- Maximum input: 2.1 × FS ≈ 81 mV
However, our load cell has a maximum output of 10 mV, which is significantly below the specified minimum calibration span.
Observed behavior:
- We tested inputs at 10 mV, 15 mV, and 30 mV.
- We begin to observe full-scale counts starting at approximately 15 mV.
- This is notably lower than the expected ~31 mV minimum based on the datasheet.
Questions:
- What could explain achieving full-scale counts at ~15 mV, which is below the specified minimum system calibration span?
- Is this behavior valid and reliable for production use, or could it lead to accuracy or stability issues?
- Given our load cell output (max 10 mV), would you recommend proceeding with AD7192, or should we consider alternative configurations or devices?
Additionally, could you please connect us with an Analog Devices application engineer to further investigate and discuss this issue in detail?
We would appreciate your guidance in understanding whether this observed behavior is within acceptable operation limits and suitable for long-term use.
