I am working with Vivado 2016.4, I have a design which implemented in system generator.
I've set the Implementation Interface on the Xilinx gateway blocks to "AXI4-Lite" which gives me the interface, however it is clocked at the rate of my waveform data generator (40 MHz). I want to separate the clock for in/out gateway, Is there anyway I can separate the clocks in system generator so that I can run the AXI4-Lite interface at 100-200MHz. while I run the waveform generation at 40 MHz?
Thank you,
Avi