Now Digital Storage Oscilloscopes have replaced completely analog oscilloscopes because of the advanced trigger, storage, display, measure functions.

As shown in figure 1, the function blocks of DSO include analog channel, ADC and digital storage, DSP, display and control. The analog channel is always composed of two high-speed amplifiers which are used to meet the demand for high gain and a variable amplifier. The input signal is amplified through the analog channel and then converted into digital signal by the high speed ADC. SDRAM stored the digital signal bits processed by FPGA, DSP extracts and processes digital signal and then pushes into the allocated display memory, finally display controller can figure out the signal image correctly.

For the above solution, the high-speed input signal conversion and storage are the key factors; but the analog channel is a little more complex than that in Figure 3.

There are two ways can give a more stable and economic solution for the high-speed input signal conversion and storage problem. Firstly, we can chose a de-multiplexer ADC to decrease the input bit rate for FPGA, then a FIFO should be created in the FPGA to guarantee the stable storage of digital signal in the SDRAM. National Semiconductor’s ADC081000 is recommended in this solution, The ADC081000 is an 8-Bit, 1 GSPS A/D converter, it can be used for DSO design with bandwidth up to 250MHz, and the converter has a 1:2 de-multiplexer that feeds two LVDS buses, which reduces the output data rate on each bus to 500Mbps. So we can create a 512*8 FIFO in the FPGA to transmit the digital signal to the SDAM reliably.
To simplify the analog channel, a single IC LMH6518SQE/NOPBLMH6518SQE/NOPB is recommended. Figure 2 is the block diagram of LMH6518SQE/NOPBLMH6518SQE/NOPB.

The LMH6518SQE/NOPBLMH6518SQE/NOPB is a variable gain amplifier that can be digitally controlled; its total gain can change by 2 dB in the range of 40dB from −1.16 dB to 38.84 dB. When collaborating with a National Semiconductor Gsample/second (Gsps) ADC with adjustable full scale range, the gain accuracy at each setting can be typically 0.1 dB. The −3 dB bandwidth can be 825 MHz at all gains, and the LMH6518SQE/NOPBLMH6518SQE/NOPB gain adjustment can deal with full scale input signals from 6.8 mVPP to 920 mVPP. The LMH6518 gain is programmed via a SPI-1 serial bus. A signal path combined gain resolution can reach 8.5 mdB when the LMH6518’s gain and the Gsps ADC’s FS input are both manipulated. Propagation Delay variation over all gain settings is typically 100 ps. 2nd/3rd order harmonic distortion is −50/−53 dBc at 100 MHz. Inputs and outputs are DC-Coupled. The outputs are differential with individual Common Mode (CM) voltage control (for Main and Auxiliary outputs) and have a selectable bandwidth limiting circuitry (common to both Main & Auxiliary) of 20, 100, 200, 350, 650 MHz, 750 MHz or full bandwidth.

So LMH6518SQE/NOPBLMH6518SQE/NOPB has enough bandwidth and gain, accompany with ADC081000, it is a good choice to simplify the analog channel. To avoid EMI, select a 200M bandwidth filter in the LMH6518SQE/NOPBLMH6518SQE/NOPB. The flowing figure 3 is the simplified analog channel DSO block diagram.

Comparing to figure 2, the solution of simplified analog channel DSO design in figure 3 can decrease EMI in the high speed channel, and the bandwidth of the channel is selectable.

Meanwhile, if the hardware design of the DSO can be simplified through suitable and optimized IC selection, the SW design becomes more important and valuable.

Reference:
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