Archaeology Resistivity Meter

Hi Ken,

This is a very interesting project with great comments from Michael and Shabaz  I did not realize how low the soil resistance typically is.  Wikipedia gives the usual values to be from 10 up to 1000 (Ω-m) though sometimes higher.

https://en.wikipedia.org/wiki/Soil_resistivity

I am jumping ahead but assuming the typical user would be an enthusiast building this themselves as a diy project, open source.  If so, that would influence the choice of components, complexity and cost. Can you describe in a bit more detail your thoughts on that?

Frank

Hi Frank

yes as you have guessed I am an enthusiast building this for myself. I belong to an amateur archaeology group and we do have access to an RM Frobisher unit, although this is somewhat restricted. We quite often carry out surveys for other groups who don’t have access to equipment, mainly because of cost. The RM Frobisher unit is in the region of £3000 currently, and that’s about the going price for this sort of equipment. To my mind it’s heavily overpriced for what it is. You will see that the ball park cost figure put in on the article by Robert Beck is about £50.00, but that was 1997. I reckon on today’s prices I could put that at maybe £150 to £200. In use the RM Frobisher unit is fairly automatic. Place the probes at C1 R1 and it takes a reading and beeps to let you know, then lift the probes and place them in C1 R2 and so on up to 20. At the end of the row there is a double beep and you would swing round and put the probe in C2 R20 and come back down. At the end of the grid there is long beep, the unit then saves all the readings to sd card and shuts down. There is facility in the software to mark trees and other obstructions as dummy readings. The one criticism I have is the menus in the software are poorly written.
The biggest shortfall in the current offerings is not having a live view. A simple on screen grid that would be populated as readings are taken. We currently have to post process usually that evening so you have no idea what you have until then. Sometimes on a grid you will have an area of interest. With these we would go back over that section, but increase the number of readings to every half a meter to improve the resolution. Easier to do when your all set up. Anyway this should hopefully give you a flavour of what’s required. The majority requirement will be in the software I guess, but I can play at that. I don’t think the electronics are that sophisticated, but they could certainly do with being updated.
Ken

Hi Frank

yes as you have guessed I am an enthusiast building this for myself. I belong to an amateur archaeology group and we do have access to an RM Frobisher unit, although this is somewhat restricted. We quite often carry out surveys for other groups who don’t have access to equipment, mainly because of cost. The RM Frobisher unit is in the region of £3000 currently, and that’s about the going price for this sort of equipment. To my mind it’s heavily overpriced for what it is. You will see that the ball park cost figure put in on the article by Robert Beck is about £50.00, but that was 1997. I reckon on today’s prices I could put that at maybe £150 to £200. In use the RM Frobisher unit is fairly automatic. Place the probes at C1 R1 and it takes a reading and beeps to let you know, then lift the probes and place them in C1 R2 and so on up to 20. At the end of the row there is a double beep and you would swing round and put the probe in C2 R20 and come back down. At the end of the grid there is long beep, the unit then saves all the readings to sd card and shuts down. There is facility in the software to mark trees and other obstructions as dummy readings. The one criticism I have is the menus in the software are poorly written.
The biggest shortfall in the current offerings is not having a live view. A simple on screen grid that would be populated as readings are taken. We currently have to post process usually that evening so you have no idea what you have until then. Sometimes on a grid you will have an area of interest. With these we would go back over that section, but increase the number of readings to every half a meter to improve the resolution. Easier to do when your all set up. Anyway this should hopefully give you a flavour of what’s required. The majority requirement will be in the software I guess, but I can play at that. I don’t think the electronics are that sophisticated, but they could certainly do with being updated.
Ken

Thanks, that is helpful.  Actually a lot of things are even cheaper today.  What about surface mount parts, FPGAs, and PCB design.  Are you comfortable with those?  I like the simple diagram that Shabaz provided.  Are you comfortable programming microcontrollers in C/C++?  I think you said at one point you were comfortable with Python.  I would think a Pi or laptop could handle the user interface and post capture data analysis in essentially real time and display results as well as give instruction and take user input.  There are good mapping and plotting libraries for Python as an example.  But personally I would do the data capture on a microcontroller as Shabaz outlined.

Hi Frank I’ve never used surface mount, but I guess it shouldn’t be that difficult to use. I’ve done a wee bit of PCB design, but again very little. I mostly built circuits from PCB’s designed in magazine articles. FPGA’s are a new one on me, so I’ll have to do a bit of reading up on them. C/C++ I’ve not programmed in at all. My original programming goes back to the usual basic, Visual Basic and I did quite a bit of database programming a few years ago in Paradox and Delphi. I have used Python and I find that ok. although I’m no expert. Looks like I will have a lot of learning to do or maybe the project will be a little beyond me.
Ken

Here are a couple of nice modern ADCs to think about:

ADS1284 from TI, very high resolution, differential inputs, programmable gain, 130 dB signal to noise ratio, but about £47 each in ones.

AD7195 from Analog devices, a mere 24 bit converter, might need input buffers but stiil with programmable gain and quite nice as well,  £11.73 each.

If you are not used to soldering sm parts go for the AD7195.

Match it to an STM32F4xx processor, it is essential that the ADC sample rate be synchronised with the DAC used to generate the drive signal.

A tiny FPGA might be helpful to do this.

The ADCs say they have SPI interfaces but it can be very hard to get a good link with a uP and control sample rates - once again the tiny FPGA can save your bacon here.

I would use a Lattice ICE40 series part, cheap and easy to code (for an FPGA) and low power.

You'll notice that simple designs use square wave excitation - this is a bad idea - sine wave excitation doesn't have all those horrible harmonics to mix with intereference signals

and leak back into the passband of your synchronous filter.

The actual filtering can be realised entirely in software (that's why we want an ADC with huge dynamic range.)

The power amplifier can be two op amps - pick the right ones and buffering might not be needed for 10mA drive current.

A standard type op amp pair (running from +/- 15V rails) can produce about 20 V RMs which is quite good.

The code on the micro will have to written in C (no support for anything else). I suggest you do only basic proecessing on the micro and have a serial port  whcih can connect it

to a Windows laptop (if you want to use Snuffler) or an RPi ( or any Linux machine) if you mean to roll your own software.

It's not hard to add a Bluetooth module for simple serial data transfer to phones or tablets.

MK

Hi Michael I’ll take a look at these, I don’t have any experience with FPGA’s so I’ll have to try and get my head around them.
Thank you for help and input, much appreciated.

Ken

Michael,

Thanks for highlighting the importance of synchronizing the DAC and ADC. It is something I have not had to worry much about before although the importance is clear in this application.  I did a quick search just now and as is sometimes the case there are a number of hits most of which are confusing, scant or not applicable. How would  you would approach it or is there a reference you can recommend?  Also since SPICE is showing up a lot recently on e14, is the excitation circuit one that would benefit from simulation first in SPICE?

Frank

Hi Frank,

Michael might have better/more cost-effective suggestions for the excitation, but maybe OPA551 could be pretty neat.. it can run from fairly high voltage rails (say) +-24V, and has lots of current capability.. just in case future modifications are needed.

I guess it's not overly expensive for this type of project, it is about $5. It could be worth simulating with a low voltage sine-wave input, and TI offer a SPICE model for download. Regarding DAC I've not looked to see what's out there, but something like 14-bit would be nice (followed by a low-pass filter.

The OPA551 would certainly do but the Iq is a bit high - 8.5mA but we only expect to put 10mA out. So we'd be paying maybe 40V * 8.5mA = 340mW just to keep the amp alive - so I'd look for a lower Iq.

I'm thinking of a differential drive using to op amps running off +/- 15V, LM7322 might do, about £2, Iq = 4mA (for the pair of amps) so Pq is 120mW for more voltage compliance (+/- 30V).

The power disiaption in the SOIC package needs some checking.

@Frank, I'll dig out the justification for a design I did a while ago (need to be in the offcie to get at it) which uses a DDS chip, a micro and an FPGA and keeps everything in synch.

The essence of it all is using a common master clock.

For single (adjustable) frequency systems like this it's best to sample over an exact number of excitation cycles with an integer number of samples (DAC and ADC) per cycle.

MK

@Frank Milburn

The example I had wasn't so helpful when I looked at it so I'll go through the numbers using the AD7195. I'll assume we use a software DDS running on a STM32F4xx using the on chip DAC.

We want operating frequencies of 20Hz - 200Hz, ideally with 1Hz or better precision for the test signal - we'll call this frequency Fts

We want a sampling rate of about 1000 samples per second for ADC and DAC (so we can use one antialiasing filter for all operating frequencies).

The ADC samples at: Fadc = Fclk/(1024 × FS[9:0]) - so we could set Fclk at 4096000 Hz and FS[9:0} (which is a register in the ADC) to 4.

We don't expect to make measurements over only one test signal cycle, the more we include the narrower the bandwidth we will detect.

Let's say we sample N cycles in each test period and that there are S samples per test.

We want an integer number of cycles in each test period (this is less important when N gets very large)

So we can say Fts = Fadc * N / S

Fadc = 1000

So Fts = 1000N / S

Since we can set N over quite a wide range there are many possibilities - if we set N = 100 we can get within about 0.2Hz at 200Hz and better at lower frequencies.

Probably a 409600 Hz clock is a bad idea, because we shall want to make it an integer fraction of the processor clock - so 4.00 MHz is fine, it does mean that can't set

exactly 200Hz  but we can get very close.

AN STM32L4R5VGT6 looks like a good bet for the processor - this can run at a core speed of 120MHz so it can easily provide a 4.0 MHz timer signal for a clock.

It has dual 12 bit DACs which can produce the DDS test signal under DMA control.

The system needs a single clock for the processor and everything is synched from this.

The ADC on the micro isn't used - it may well be possible to interface the AD7195 without an FPGA - I haven't checked that (yet).

MK

Hi Michael Not sure about the frequencies in use. Is this the frequency of the square wave to generate pseudo AC. If so the original article talks about 137Hz  being the ideal, because of possible interference from 50/60Hz mains hum, and the need to filter out these frequencies later.
Not sure if i’m right or talking rubbish. Slap my wrists if I am.
I’ve also seen talk of LTSpice for simulation. I have used this, but quite a while ago. I’ll download it again and try to follow what you are doing.

All very interesting and once again thank you.

Ken

This is the test signal but it really should not be a square wave but a sine wave - the design I'm suggesting uses sine waves and decodes the measured signal by multiplying by sin and cos rather than +/- 1.

(I know that the DIY design uses a square wave and possibly some commercial devices do but it is a very bad idea. - with modern processors and electronics there really is no justification for not using a sine wave.

A square wave generator and rectangular de- modulator is sensitive to odd harmonics of the operating frequency - which makes it much harder to pick a good operating frequency.)

There is no perfect frequency -  the best to use depends on local interference conditions so I'm suggesting be able to set the frequency in the range 20Hz to 200Hz which more than covers the range that most commercial devices offer.

Re. the FPGA - it may not be necessary

MK