Archaeology Resistivity Meter

Hi Frank,

Michael might have better/more cost-effective suggestions for the excitation, but maybe OPA551 could be pretty neat.. it can run from fairly high voltage rails (say) +-24V, and has lots of current capability.. just in case future modifications are needed.

I guess it's not overly expensive for this type of project, it is about $5. It could be worth simulating with a low voltage sine-wave input, and TI offer a SPICE model for download. Regarding DAC I've not looked to see what's out there, but something like 14-bit would be nice (followed by a low-pass filter.

The OPA551 would certainly do but the Iq is a bit high - 8.5mA but we only expect to put 10mA out. So we'd be paying maybe 40V * 8.5mA = 340mW just to keep the amp alive - so I'd look for a lower Iq.

I'm thinking of a differential drive using to op amps running off +/- 15V, LM7322 might do, about £2, Iq = 4mA (for the pair of amps) so Pq is 120mW for more voltage compliance (+/- 30V).

The power disiaption in the SOIC package needs some checking.

@Frank, I'll dig out the justification for a design I did a while ago (need to be in the offcie to get at it) which uses a DDS chip, a micro and an FPGA and keeps everything in synch.

The essence of it all is using a common master clock.

For single (adjustable) frequency systems like this it's best to sample over an exact number of excitation cycles with an integer number of samples (DAC and ADC) per cycle.

MK

@Frank Milburn

The example I had wasn't so helpful when I looked at it so I'll go through the numbers using the AD7195. I'll assume we use a software DDS running on a STM32F4xx using the on chip DAC.

We want operating frequencies of 20Hz - 200Hz, ideally with 1Hz or better precision for the test signal - we'll call this frequency Fts

We want a sampling rate of about 1000 samples per second for ADC and DAC (so we can use one antialiasing filter for all operating frequencies).

The ADC samples at: Fadc = Fclk/(1024 × FS[9:0]) - so we could set Fclk at 4096000 Hz and FS[9:0} (which is a register in the ADC) to 4.

We don't expect to make measurements over only one test signal cycle, the more we include the narrower the bandwidth we will detect.

Let's say we sample N cycles in each test period and that there are S samples per test.

We want an integer number of cycles in each test period (this is less important when N gets very large)

So we can say Fts = Fadc * N / S

Fadc = 1000

So Fts = 1000N / S

Since we can set N over quite a wide range there are many possibilities - if we set N = 100 we can get within about 0.2Hz at 200Hz and better at lower frequencies.

Probably a 409600 Hz clock is a bad idea, because we shall want to make it an integer fraction of the processor clock - so 4.00 MHz is fine, it does mean that can't set

exactly 200Hz  but we can get very close.

AN STM32L4R5VGT6 looks like a good bet for the processor - this can run at a core speed of 120MHz so it can easily provide a 4.0 MHz timer signal for a clock.

It has dual 12 bit DACs which can produce the DDS test signal under DMA control.

The system needs a single clock for the processor and everything is synched from this.

The ADC on the micro isn't used - it may well be possible to interface the AD7195 without an FPGA - I haven't checked that (yet).

MK

Hi Michael Not sure about the frequencies in use. Is this the frequency of the square wave to generate pseudo AC. If so the original article talks about 137Hz  being the ideal, because of possible interference from 50/60Hz mains hum, and the need to filter out these frequencies later.
Not sure if i’m right or talking rubbish. Slap my wrists if I am.
I’ve also seen talk of LTSpice for simulation. I have used this, but quite a while ago. I’ll download it again and try to follow what you are doing.

All very interesting and once again thank you.

Ken

Hi Shabaz

I’ll order one of the FPGA training boards so I can get my mind around them.

Thank you

Ken

This is the test signal but it really should not be a square wave but a sine wave - the design I'm suggesting uses sine waves and decodes the measured signal by multiplying by sin and cos rather than +/- 1.

(I know that the DIY design uses a square wave and possibly some commercial devices do but it is a very bad idea. - with modern processors and electronics there really is no justification for not using a sine wave.

A square wave generator and rectangular de- modulator is sensitive to odd harmonics of the operating frequency - which makes it much harder to pick a good operating frequency.)

There is no perfect frequency -  the best to use depends on local interference conditions so I'm suggesting be able to set the frequency in the range 20Hz to 200Hz which more than covers the range that most commercial devices offer.

Re. the FPGA - it may not be necessary

MK

Thanks Michael, good explanation. I get it now.  Simpler than I thought.

EDIT:  that is, simpler except for the FPGA :-). I’ve never used FPGAs.

I'm hoping this application can avoid an FPGA, the ADC can talk directly to the processor - it'll need an interrupt every 1ms but the 120MHz STM32l4xxxx can cope with that.

But happy to help put an FPGA in just for the fun of it

MK

I don't know whether to welcome a FPGA as a learning experience or be terrified.  They don't have a reputation for being beginner friendly  

Hehe my vote is stick the FPGA in : )

It could be nice to offload that portion, gets people more interested in FPGA, plus the processor code will be slightly simplified and more portable for future people to use different or less performance devices or experiment/modify. In theory since then there's very little timing concern for the processor, some people could rip out the processor and use a Pi and a process on Linux (not that I'm suggesting it is a good idea, but technically possible) to prototype code enhancements too.