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BeagleBoard-X15: new OSHW from BeagleBoard.org

fustini

Official announcement today from & BeagleBoard.org:

 

image

BeagleBoard.org - 2015-10-14-beagleboard-x15

Announcing the new powerful BeagleBoard-X15 open hardware computer for electronics innovators from BeagleBoard.org

Innovate with an open community of developers on the most powerful and flexible open hardware computer development system available

 

 

 

 

 

Powered by a SitaraTm AM572x processor from Texas Instruments (TI) [...] dual ARMRegistered CortexRegistered-A15 cores clocked at 1.5GHz [...] Accelerated processing of physical world data is made easier than ever with the dual C66x digital signal processors (DSPs) supported by OpenCL

 

 

There is a form to register your interest in BeagleBoard-X15 for delivery in time for Christmas:


http://beagleboard.org/X15

 

 

Here the wiki page with more details:

 

Beagleboard:BeagleBoard-X15 - eLinux.org

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  • John Beetem makes a good point, we are seeing other processors that are multi-cored, and so I got curious about the secret sauce that holds everything together.

    According to the TRM, there is a full-blown switching fabric type of interconnect (called L3 interconnect in there, but means 'level 3' not layer 3) from Arteris inside the chip (not used between the ARM Cortex-A cores, but between the different cores and other major subsystems). No idea on throughput capability, but given it is 128-bit wide and non-blocking according to a deepchip post it could be a spectacular amount of throughput between modules simultaneously. Some of the modules appear to have multiple 128-bit wide interconnects to the fabric. All the other peripherals are connected into this fabric at high speed from L4 (level 4, not layer 4) interconnect modules.


    There is some cool functionality like the ability to have bandwidth regulation, priorities and some security features.

    It will take some study though - 260 pages of documentation on the interconnect alone!

  • in reply to shabaz

    shabaz wrote:

     

    No idea on throughput capability, but given it is 128-bit wide and non-blocking according to a deepchip post it could be a spectacular amount of throughput between modules simultaneously. Some of the modules appear to have multiple 128-bit wide interconnects to the fabric. All the other peripherals are connected into this fabric at high speed from L4 (level 4, not layer 4) interconnect modules.


    There is some cool functionality like the ability to have bandwidth regulation, priorities and some security features.

    Obviously not cool in the thermal sense, given the heat sink image  OTOH, I did amuse Gerald Coley by sticking a heat sink on my original BeagleBoard B4.

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  • in reply to shabaz

    shabaz wrote:

     

    No idea on throughput capability, but given it is 128-bit wide and non-blocking according to a deepchip post it could be a spectacular amount of throughput between modules simultaneously. Some of the modules appear to have multiple 128-bit wide interconnects to the fabric. All the other peripherals are connected into this fabric at high speed from L4 (level 4, not layer 4) interconnect modules.


    There is some cool functionality like the ability to have bandwidth regulation, priorities and some security features.

    Obviously not cool in the thermal sense, given the heat sink image  OTOH, I did amuse Gerald Coley by sticking a heat sink on my original BeagleBoard B4.

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