There are a lot of topological possibilities for a circuit that creates a delay. Let me abstract this discussion a little bit from your application. You can extend the delay period for just about any setup that uses a timing capacitor which has one side attached to the supply with a capacitance multiplier circuit, which is just a few Rs and an op-amp. You can learn something about e- by building it and seeing how it works. 100x extension on time is easily achievable this way.
Without such tricks and with ordinary components, it is hard to fab delay circuits that take longer than c. 10 s.
Alternately, you could use a counter (w F/F and osc) to achieve multiples of your intrinsic delay.
Commodity comparators and 555s cost about the same, though you get a 3R string and a F/F on the 555. Even if you use a 555 you should be careful to 'think inside the chip' to understand its functions. You can always make a F/F out of a pair of gates if that is convenient.
There are a lot of topological possibilities for a circuit that creates a delay. Let me abstract this discussion a little bit from your application. You can extend the delay period for just about any setup that uses a timing capacitor which has one side attached to the supply with a capacitance multiplier circuit, which is just a few Rs and an op-amp. You can learn something about e- by building it and seeing how it works. 100x extension on time is easily achievable this way.
Without such tricks and with ordinary components, it is hard to fab delay circuits that take longer than c. 10 s.
Alternately, you could use a counter (w F/F and osc) to achieve multiples of your intrinsic delay.
Commodity comparators and 555s cost about the same, though you get a 3R string and a F/F on the 555. Even if you use a 555 you should be careful to 'think inside the chip' to understand its functions. You can always make a F/F out of a pair of gates if that is convenient.
