AMIC - A25L010-F - MEMORY, FLASH, SPI, 1M, 8DIP

AMIC - A25L010-FA25L010-F - MEMORY, FLASH, SPI, 1M, 8DIP | Buy Now!Buy Now!

A25L020/A25L010/A25L512 Series

2Mbit / 1Mbit / 512Kbit Low Voltage, Serial Flash Memory

With 100MHz Uniform 4KB Sectors

Product Description

The A25L020/A25L010/A25L512 are 2M/1M/512K bit Serial Flash Memory, with advanced write protection mechanisms, accessed by a high speed SPI-compatible bus. The memory can be programmed 1 to 256 bytes at a time, using the Page Program instruction.

The memory is organized as 4/2/1(A25L020/A25L010/A25L512) blocks, each containing 16 sectors. Each sector is composed of 16 pages. Each page is 256 bytes wide. Thus, the whole memory can be viewed as consisting of 1024/512/256 (A25L020/A25L010/A25L512) pages, or 262,144/131,072/

65,536 (A25L020/A25L010/A25L512) bytes.

The whole memory can be erased using the Chip Erase instruction, a block at a time, using Block Erase instruction, or a sector at a time, using the Sector Erase instruction.

Product Features

Family of Serial Flash Memories

- A25L020: 2M-bit /256K-byte

- A25L010: 1M-bit /128K-byte

- A25L512: 512K-bit /64K-byte

Flexible Sector Architecture with 4KB sectors

- Sector Erase (4K-bytes) in 0.2s (typical)

- Block Erase (64K-bytes) in 0.5s (typical)

Page Program (up to 256 Bytes) in 2ms (typical)

1. 2.7 to 3.6V Single Supply Voltage

SPI Bus Compatible Serial Interface

100MHz Clock Rate (maximum)

Deep Power-down Mode 25μA (Max.)

Stand-by current 25μA (Max.)

Electronic Signatures

- JEDEC Standard Two-Byte Signature

A25L020 (3012h)

A25L010 (3011h)

A25L512 (3010h)

- RES Instruction, One-Byte, Signature, for backward compatibility

A25L020 (11h)

A25L010 (10h)

A25L512 (05h)

Package options

- 8-pin SOP (150/209mil), 8-pin DIP (300mil), 8-pin TSSOP

(A25L010V-F/A25L512V-F), 8-pin USON (2*3mm) and 8-pin WSON (6*5mm)

- All Pb-free (Lead-free) products are RoHS compliant

Signal Description

• Serial Data Output (DO). This output signal is used to transfer data serially out of the device. Data is shifted out onthe falling edge of Serial Clock (C).
• The DO pin is also used as an input pin when the Fast Read
• Dual Input-Output instruction is executed.
• Serial Data Input (DIO). This input signal is used to transfer data serially into the device. It receives instructions, addresses, and the data to be programmed. Values are latched on the rising edge of Serial Clock (C).
• The DIO pin is also used as an output pin when the Fast
• Read Dual Output instruction and the Fast Read Dual
• Input-Output instruction are executed.
• Serial Clock (C). This input signal provides the timing of the serial interface. Instructions, addresses, or data present at Serial Data Input (DIO) are latched on the rising edge of Serial Clock (C). Data on Serial Data Output (DO) changes after the falling edge of Serial Clock (C).
• Chip Select (S ). When this input signal is High, the device is deselected and Serial Data Output (DO) is at high impedance. Unless an internal Program, Erase or Write
• Status Register cycle is in progress, the device will be in the Standby mode (this is not the Deep Power-down mode).
• Driving Chip Select (S) Low enables the device, placing it in the active power mode.
• After Power-up, a falling edge on Chip Select (S) is required prior to the start of any instruction.
• Hold (HOLD ). The Hold (HOLD) signal is used to pause any serial communications with the device without deselecting the device.
• During the Hold condition, the Serial Data Output (DO) is high impedance, and Serial Data Input (DIO) and Serial Clock (C) are Don’t Care. To start the Hold condition, the device must be selected, with Chip Select (S) driven Low.
• Write Protect (W). The main purpose of this input signal is to freeze the size of the area of memory that is protected against program or erase instructions (as specified by the values in the BP2, BP1, and BP0 bits of the Status Register).