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PSK detection via DSP

Former Member

I am looking for reference materials to assist in developing a BPSK detector operating in the audio range. The detector is to be implemented as code in a DSP. The detector operates using a discrete PLL at present, I looking for a solution which reduces the hardware and gives a better development path, without significant power increase. Any suggestions?

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  • BPSK (Binary phase shift keying) is actually pretty easy to demodulate. You need three things:

     

    1. A local oscillator that is the same frequency and phase of the incoming signal (or coherent)
    2. A multiplier (a mixer in hardware terms)
    3. A low pass filter

     

    The local oscillator is the tough part.  You will need to build a PLL into your code that uses DDS (Direct Digital Synthesis) to create a sine wave that is the same frequency and phase as the incoming signal (in other words, the LO crosses zero at the same time as the incoming signal).  Once you have that, you literally multiply it by the incoming signal.  The output will an NRZ signal that goes high when the input is in one phase and low when it is in the other phase.

     

    The trick here is that you never know what the relationship between phase and the NRZ signal is.  It totally depends on the LO and how it syncs.  So you can't say, for example that 0 degrees is a one and 180 degrees is a zero.  Your protocol needs to provide a way to determine the relationship at the beginning of a packet.

     

    Once you have your NRZ signal, it will have multiplication noise on it because the input signal is not perfect... it is noisy.  So you LPF the signal so that only the data rate is allowed through.  Normally, I would corner that LPF at 1.5-2.0 of the data ratex2.

     

    If you want more details, check out this PDF, it is pretty good.  If you need any help with putting this into code, ask away.  I have experience coding DSPs, especially in the audio band, and I have a good background in wireless comms.

     

    http://hal.archives-ouvertes.fr/docs/00/34/75/10/PDF/WSEAS2007BPSK.pdf

     

    Regards,

    Steve The RF Guy

    "May God bless everything you do"

Reply

  • BPSK (Binary phase shift keying) is actually pretty easy to demodulate. You need three things:

     

    1. A local oscillator that is the same frequency and phase of the incoming signal (or coherent)
    2. A multiplier (a mixer in hardware terms)
    3. A low pass filter

     

    The local oscillator is the tough part.  You will need to build a PLL into your code that uses DDS (Direct Digital Synthesis) to create a sine wave that is the same frequency and phase as the incoming signal (in other words, the LO crosses zero at the same time as the incoming signal).  Once you have that, you literally multiply it by the incoming signal.  The output will an NRZ signal that goes high when the input is in one phase and low when it is in the other phase.

     

    The trick here is that you never know what the relationship between phase and the NRZ signal is.  It totally depends on the LO and how it syncs.  So you can't say, for example that 0 degrees is a one and 180 degrees is a zero.  Your protocol needs to provide a way to determine the relationship at the beginning of a packet.

     

    Once you have your NRZ signal, it will have multiplication noise on it because the input signal is not perfect... it is noisy.  So you LPF the signal so that only the data rate is allowed through.  Normally, I would corner that LPF at 1.5-2.0 of the data ratex2.

     

    If you want more details, check out this PDF, it is pretty good.  If you need any help with putting this into code, ask away.  I have experience coding DSPs, especially in the audio band, and I have a good background in wireless comms.

     

    http://hal.archives-ouvertes.fr/docs/00/34/75/10/PDF/WSEAS2007BPSK.pdf

     

    Regards,

    Steve The RF Guy

    "May God bless everything you do"

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  • in reply to Former Member

    Many Thanks Steve, I will come back to you when I start the coding. I have a hardware pll working at present and will be trying to get some sci-lab simulations (My company can't stretch to the simulink investment yet) working so that I have a good grip on the system before the coding begins. Have you any experience on using the Costas loop in this type of application? I attempted one with linear multipliers and could not get it to perform consistantly.

    Thanks again

     

    Bill

  • in reply to Former Member

    Steve,

     

    A little bit more information has surfaced while digging around trying to select an appropriate DSP chip for the task, I have been looking at the 320F2812 for various reasons and I found two very relevant application notes, SPRU714 and SPRAAD5. I have yet to find the code to go with these documents but they come as a close match to techniques which apply. I am not convinced about the sample rate for my environment, which is very low SNR, but at present that is a detail.

     

    Regards

    Bill