Wireless switch for power

Typically, to energize a moderate load in a single-ended manner, like on-off we can use an N-channel mosfet.  Since we have our choice of P or N, and since, in Si, N is perkier than P as a charge-carrier, we go N thus finding ourselves pulling down to activate our load.  This is a three-terminal enhancement-mode device.  There is a main conduction channel.  Drain in our Nchan is the topside connection of the channel, Source is the lower end, typically connected to the bottom of a unipolar voltage supply.  Typically it goes: top-of-supply -> top-of-load -> bottom of load -> drain | source -> bottom of supply.  The third terminal of the mosfet is the gate, which modulates the conductivity of the channel.  I should mention that there is a backward diode in shunt with the main conduction channel, just hangin' about.  These devices are just ok in a linear mode, as an aside pos tempco.  Where they shine is switchmode.  Bringing the gate (gate potential relative to drain potential) above Vgs-th, (as a practical manner with some margin) and our channel is enhanced so as to be conductive as the bulk Si.electrically connecting Drain and Source, save Ron.  Breakdown voltage of the channel is a critical param, and comes with the cost of higher Ron.  Slewing the gate to ground turns the channel quite off.  The gate is rather capacitive, so at frequencies associated with SMPS, we need buffers to dump the gate charge quickly.  But for any likely frequency useful in a device such as a solenoid, we don't have to worry about gate-charge too much.  If our load is purely resistive, BV doesn't have to be much greater than supply potential.  For inductive loads, typically some kind of snubbing is required to minimize kickback spikes, and more margin in terms of BV is wise.  Modeling in SPICE works great here, but drag out the o-scope for final conformance verification.  For capacitive loads or thermally reactive loads, inrush limiting should be considered.

An excellent driver for a typical Mosfet would be a TLP351 saturating opto-isolator with CMOS output.  7/800 Ampere into the input led drives the output high.  Were this attach to the gate of a typical (mind gate BV) mosfet the conduction channel would go to a low-Z state.  The nature of the output structure of this iso makes for quick transitions both on-off and off-on.  In the SMPS situation one might insert a preamp:  Tiny NPN collector tied high, tiny PNP collector tied low.  Emitters bussed as output to gate of mosfet, bases bussed as input and attached to optoisolator output.

To compute the 8.75 mA for the input diode, first making sure that one's CV doesn't need a buffer, noting we have both ends of the diode so we can pull up or pull down as we please, lets guess the input diode drop is 1.2V, and, say, a 3.3 V supply gives me a 1.1 drop across my ballast R presuming an ideal logic driver to the left.  V=IR, so R=V/I, 1.1/8.75/K ~ 125 Ohms.

Typically, to energize a moderate load in a single-ended manner, like on-off we can use an N-channel mosfet.  Since we have our choice of P or N, and since, in Si, N is perkier than P as a charge-carrier, we go N thus finding ourselves pulling down to activate our load.  This is a three-terminal enhancement-mode device.  There is a main conduction channel.  Drain in our Nchan is the topside connection of the channel, Source is the lower end, typically connected to the bottom of a unipolar voltage supply.  Typically it goes: top-of-supply -> top-of-load -> bottom of load -> drain | source -> bottom of supply.  The third terminal of the mosfet is the gate, which modulates the conductivity of the channel.  I should mention that there is a backward diode in shunt with the main conduction channel, just hangin' about.  These devices are just ok in a linear mode, as an aside pos tempco.  Where they shine is switchmode.  Bringing the gate (gate potential relative to drain potential) above Vgs-th, (as a practical manner with some margin) and our channel is enhanced so as to be conductive as the bulk Si.electrically connecting Drain and Source, save Ron.  Breakdown voltage of the channel is a critical param, and comes with the cost of higher Ron.  Slewing the gate to ground turns the channel quite off.  The gate is rather capacitive, so at frequencies associated with SMPS, we need buffers to dump the gate charge quickly.  But for any likely frequency useful in a device such as a solenoid, we don't have to worry about gate-charge too much.  If our load is purely resistive, BV doesn't have to be much greater than supply potential.  For inductive loads, typically some kind of snubbing is required to minimize kickback spikes, and more margin in terms of BV is wise.  Modeling in SPICE works great here, but drag out the o-scope for final conformance verification.  For capacitive loads or thermally reactive loads, inrush limiting should be considered.

An excellent driver for a typical Mosfet would be a TLP351 saturating opto-isolator with CMOS output.  7/800 Ampere into the input led drives the output high.  Were this attach to the gate of a typical (mind gate BV) mosfet the conduction channel would go to a low-Z state.  The nature of the output structure of this iso makes for quick transitions both on-off and off-on.  In the SMPS situation one might insert a preamp:  Tiny NPN collector tied high, tiny PNP collector tied low.  Emitters bussed as output to gate of mosfet, bases bussed as input and attached to optoisolator output.

To compute the 8.75 mA for the input diode, first making sure that one's CV doesn't need a buffer, noting we have both ends of the diode so we can pull up or pull down as we please, lets guess the input diode drop is 1.2V, and, say, a 3.3 V supply gives me a 1.1 drop across my ballast R presuming an ideal logic driver to the left.  V=IR, so R=V/I, 1.1/8.75/K ~ 125 Ohms.