来源 ：中电网
Cypress 公司的CY8CPLC20是集成了动力线调制解调器PHY和网络协议堆栈的动力线通信（PLC）芯片，具有功能强大的哈佛架构处理器，其中的M8C处理器的速度高达24MHz，支持I2C频率50kHz，100kHz和400kHz，支持双向半双工通信。本文介绍了CY8CPLC20主要特性，逻辑方框图，物理层FSK调制解调器方框图，PSoC核方框图以及PLC CY3275CY3275 低压（LV）开发板主要特性，方框图和电路图。
The CY8CPLC20 is an integrated Powerline Communication (PLC) chip with the Powerline Modem PHY and Network Protocol Stack running on the same device. Apart from the PLC core, the CY8CPLC20 also offers Cypress’s revolutionary PSoC technology that enables system designers to integrate multiple functions on the same chip.
CY8CPLC20主要特性：
■ Powerline Communication Solution
❐ Integrated Powerline Modem PHY
❐ Frequency Shift Keying Modulation
❐ Configurable baud rates up to 2400 bps
❐ Powerline Optimized Network Protocol
❐ Integrates Data Link, Transport, and Network Layers
❐ Supports Bidirectional Half Duplex Communication
❐ 8-bit CRC Error Detection to Minimize Data Loss
❐ I2C enabled Powerline Application Layer
❐ Supports I2C Frequencies of 50, 100, and 400 kHz
❐ Reference Designs for 110V/240V AC and 12V/24V AC/DC Powerlines
❐ Reference Designs comply with CENELEC EN 50065-1:2001 and FCC Part 15
■ Powerful Harvard Architecture Processor
❐ M8C Processor Speeds to 24 MHz
❐ Two 8x8 Multiply, 32-Bit Accumulate
■ Programmable System Resources (PSoC
Blocks)
❐ 12 Rail-to-Rail Analog PSoC Blocks provide:
• Up to 14-Bit ADCs
• Up to 9-Bit DACs
• Programmable Gain Amplifiers
• Programmable Filters and Comparators
❐ 16 Digital PSoC Blocks provide:
• 8 to 32-Bit Timers, Counters, and PWMs
• CRC and PRS Modules
• Up to Four Full Duplex UARTs
• Multiple SPI
Masters or Slaves
• Connectable to all GPIO Pins
❐ Complex Peripherals by Combining Blocks
■ Flexible On-Chip Memory
❐ 32 KB Flash Program Storage 50,000 Erase or Write Cycles
❐ 2 KB SRAM Data Storage
❐ EEPROM Emulation in Flash
■ Programmable Pin Configurations
❐ 25 mA Sink, 10 mA Source on all GPIO
❐ Pull Up, Pull Down, High Z, Strong, or Open Drain Drive Modes on all GPIO
❐ Up to 12 Analog Inputs on GPIO
❐ Configurable Interrupt on all GPIO
■ Additional System Resources
❐ I2C Slave, Master, and Multi-Master to 400 kHz
❐ Watchdog and Sleep Timers
❐ User-Configurable Low Voltage Detection
❐ Integrated Supervisory Circuit
❐ On-Chip Precision Voltage Reference
■ Complete Development Tools
❐ Free Development Software (PSoC Designer)
❐ Full Featured In-Circuit Emulator (ICE) and Programmer
❐ Full Speed Emulation
❐ Complex Breakpoint Structure
❐ 128 KB Trace Memory
❐ Complex Events
❐ C Compilers, Assembler, and Linker
图1。CY8CPLC20逻辑方框图
图2。CY8CPLC20物理层FSK调制解调器方框图
图3。CY8CPLC20 PSoC核方框图
PLC CY3275CY3275 低压（LV）开发板
The PLC CY3275CY3275 Low Voltage (LV) development board allows system design using the ability of the Cypress PLC family of devices to transmit data up to 2400 bps over low voltage (12V to 24V AC/DC) powerlines.
Powerlines are available everywhere in the world. This makes them one of the most widely available communication mediums for PLC technology. The pervasiveness of powerlines also makes it difficult to predict their characteristics and noise. Because of the variability of powerline quality, implementing robust communication over powerline has been an engineering challenge for years. With this in mind, the Cypress PLC solution is designed to enable secure, reliable, and robust communication over powerlines.
PLC CY3275CY3275 低压（LV）开发板主要特性：
The key features of the Cypress PLC solution are:
■ An integrated powerline PHY modem with optimized amplifiers that work with rugged high and low voltage powerlines
■ Powerline optimized network protocol that supports bidirectional communication with acknowledgement based signaling and multiple retries
■ Support for 8-bit packet CRC and 4-bit header CRC for error detection and data packet retransmission
■ Carrier Sense Multiple Access (CSMA) scheme that minimizes collisions between packet transmissions on the powerline
PLC CY3275CY3275 低压（LV）开发板包括：
The CY3275CY3275 PLC LV Development kit contains:
■ CY3275CY3275 PLC LV development board
■ CY3275CY3275 Quick start guide
■ CD-ROM containing:
❐ Packet Test software – PLC Control Panel application
❐ CY8CPLC20 data sheet
❐ User guide
❐ CY3275CY3275 Board Altium design project
❐ CY3275CY3275 Board BOM
❐ Application note – Using CY8CPLC20 in Powerline Communication (PLC) Applications
❐ CY3275CY3275 Board schematics
❐ CY3275CY3275 Board Gerbers
❐ PSoC Designer
❐ PSoC Programmer
■ 12V DC power supply
■ MiniProg1 for programming the CY8CPLC20 device
■ 25 Jumper wires
■ LCD module
■ USB-I2C Bridge
■ Retractable USB cable
■ Daisy chain cable
The Cypress CY3275CY3275 LV CY8CPLC20 development board is a versatile tool with these features
■ User friendly PLC Control Panel application available on the kit CD-ROM
■ Chip power supply derived from 12V to 24V AC/DC
■ CY8CPLC20-OCD chip -- 100-pin TQFP on chip debug (OCD) device that allows for the quick design and debug of PLC applications. The CY8CPLC20 100-pin TQFP is available for debug purposes only. For production quantities, CY8CPLC20 is available in 28-pin SSOP and 48-pin QFN packages.
■ User configurable general purpose LEDs
■ General purpose 8-bit DIP switch
■ RJ45 connector to use ICE debugger
■ RS232 COM port for serial communication
■ Header to attach LCD card
■ I2C header for communicating to external devices
■ ISSP header for programming the CY8CPLC20 chip
图4。PLC 解决方案方框图
图5。PLC 系统级方框图-两个节点
图6。PLC LV开发板外形图（顶视图）
图7。PLC LV开发板电路图-用户接口
图8。PLC LV开发板电路图-发送和接收滤波器耦合
图9。PLC LV开发板电路图-电源